#include "hb_ddr_oem.h"
#include "x3_info.h"

struct ddr_dfs_freqs lpddr4_samsung_1g[] = {
	{DDR_FREQC_3200, DDR_FREQC_1333, DDR_FREQC_333},
	{DDR_FREQC_2666, DDR_FREQC_1333, DDR_FREQC_333},
};
unsigned int lpddr4_samsung_1g_cnt = ARRAY_SIZE(lpddr4_samsung_1g);

struct ddr_dfs_freqs lpddr4_samsung_2g[] = {
	{DDR_FREQC_3200, DDR_FREQC_1333, DDR_FREQC_333},
};
unsigned int lpddr4_samsung_2g_cnt = ARRAY_SIZE(lpddr4_samsung_2g);

/*JH XG 2G DFS */
struct ddr_dfs_freqs lpddr4_3200_333[] = {
	{DDR_FREQC_3200, DDR_FREQC_333, 0},
};
unsigned int lpddr4_3200_333_cnt = ARRAY_SIZE(lpddr4_3200_333);

struct DRAM_CFG_PARAM ddr4_ddrc_cfg[] = {
	/* Start to config, default 3200mbps */
	{uMCTL2_MSTR, 0x83040010},
	{uMCTL2_MRCTRL0, 0x40004030},
	{uMCTL2_MRCTRL1, 0x2d11d},
	{uMCTL2_MRCTRL2, 0xc21162f7},
	{uMCTL2_DERATEEN, 0x1404},
	{uMCTL2_DERATEINT, 0x109a928d},
	{uMCTL2_MSTR2, 0x1},
	{uMCTL2_DERATECTL, 0x1},
	{uMCTL2_PWRCTL, 0x0},
	{uMCTL2_PWRTMG, 0x40fa04},
	{uMCTL2_HWLPCTL, 0x730002},
	{uMCTL2_RFSHCTL0, 0x210000},
	{uMCTL2_RFSHCTL1, 0x920016},
	{uMCTL2_RFSHCTL3, 0x1},
	{uMCTL2_RFSHTMG, 0xc30118},
	{uMCTL2_RFSHTMG1, 0x40000},
	{uMCTL2_ECCCFG0, 0x403f02d4},//1/16(1)
	{uMCTL2_ECCCFG0, 0x33f7f10},
	{uMCTL2_ECCCFG1, 0x790},
	{uMCTL2_ECCCTL, 0x700},
	{uMCTL2_ECCPOISONADDR0, 0x0},
	{uMCTL2_ECCPOISONADDR1, 0x0},
	{uMCTL2_CRCPARCTL0, 0x0},
	{uMCTL2_CRCPARCTL1, 0x0},
	{uMCTL2_INIT0, 0xc0020002},
	{uMCTL2_INIT1, 0x10002},
	{uMCTL2_INIT2, 0xa0a},
	{uMCTL2_INIT3, 0xc450201},
	{uMCTL2_INIT4, 0x280400},
	{uMCTL2_INIT5, 0x11018c},
	{uMCTL2_INIT6, 0x0480},
	{uMCTL2_INIT7, 0x1018},
	{uMCTL2_DIMMCTL, 0x0},
	{uMCTL2_RANKCTL, 0x2bf},
	{uMCTL2_DRAMTMG0, 0x1618361a},
	{uMCTL2_DRAMTMG1, 0x50624},
	{uMCTL2_DRAMTMG2, 0x80a0512},
	{uMCTL2_DRAMTMG3, 0x400c},
	{uMCTL2_DRAMTMG4, 0xa04060b},
	{uMCTL2_DRAMTMG5, 0x90d0504},
	{uMCTL2_DRAMTMG6, 0x0},
	{uMCTL2_DRAMTMG7, 0x808},
	{uMCTL2_DRAMTMG8, 0x9096b0b},
	{uMCTL2_DRAMTMG9, 0x2050e},
	{uMCTL2_DRAMTMG10, 0xe0c0a},
	{uMCTL2_DRAMTMG11, 0x1a0b010e},
	{uMCTL2_DRAMTMG12, 0x10},
	{uMCTL2_DRAMTMG13, 0x0},
	{uMCTL2_DRAMTMG14, 0x0},
	{uMCTL2_DRAMTMG15, 0x80000000},
	{uMCTL2_ZQCTL0, 0xc1000040},
	//{uMCTL2_ZQCTL0, 0x51000040},
	{uMCTL2_ZQCTL1, 0x9aa3c},
	{uMCTL2_ZQCTL2, 0x0},
	{uMCTL2_DFITMG0, 0x48f820b},
	{uMCTL2_DFITMG1, 0x3090303},
	{uMCTL2_DFILPCFG0, 0x360b010},
	{uMCTL2_DFILPCFG1, 0x41},
	{uMCTL2_DFIUPD0, 0x80400018},
	{uMCTL2_DFIUPD1, 0xbe00e8},
	{uMCTL2_DFIUPD2, 0x0},
	{uMCTL2_DFIMISC, 0x41},
	{uMCTL2_DFITMG2, 0xf0b},
	{uMCTL2_DFITMG3, 0x8},
#if ( (RD_DBI_EN == 1) && (WR_DBI_EN_DDR4==1) )
	{uMCTL2_DBICTL, (RD_DBI_EN<<2 | WR_DBI_EN_DDR4<<1)}, //0x6},
#elif ( RD_DBI_EN == 1 )
	{uMCTL2_DBICTL, 0x5},
#elif ( WR_DBI_EN_DDR4== 1 )
	{uMCTL2_DBICTL, 0x2},
#else
	{uMCTL2_DBICTL, 0x1},
#endif
	{uMCTL2_DFIPHYMSTR, 0x0},
	{uMCTL2_ADDRMAP0, 0x17},
	{uMCTL2_ADDRMAP1, 0x3f0808},
	{uMCTL2_ADDRMAP2, 0x0},
	{uMCTL2_ADDRMAP3, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_ADDRMAP5, 0x70f0707},
	{uMCTL2_ADDRMAP6, 0x7070707},
	{uMCTL2_ADDRMAP7, 0xf0f},
	{uMCTL2_ADDRMAP8, 0x3f0a},
	{uMCTL2_ADDRMAP9, 0x7070707},
	{uMCTL2_ADDRMAP10, 0x7070707},
	{uMCTL2_ADDRMAP11, 0x7},
	{uMCTL2_ODTCFG, 0x6060618},
	{uMCTL2_ODTMAP, 0x2201},
	{uMCTL2_SCHED, 0x20003601},
	{uMCTL2_SCHED1, 0x0},
	{uMCTL2_PERFHPR1, 0xf000001},
	{uMCTL2_PERFLPR1, 0xf00007f},
	{uMCTL2_PERFWR1, 0xf00007f},
	{uMCTL2_DBG0, 0x0},
	{uMCTL2_DBG1, 0x0},
	{uMCTL2_DBGCMD, 0x0},
	{uMCTL2_SWCTL, 0x1},
	{uMCTL2_SWCTLSTATIC, 0x0},
	{uMCTL2_POISONCFG, 0x10000},
	{uMCTL2_ADVECCINDEX, 0x62},
	{uMCTL2_ECCPOISONPAT0, 0x0},
	{uMCTL2_ECCPOISONPAT2, 0x0},
	{uMCTL2_PCCFG, 0x101},
	{uMCTL2_PCFGR_0, 0x707f},
	{uMCTL2_PCFGW_0, 0x707f},
	{uMCTL2_PCFGQOS0_0, 0x02200a08},
	{uMCTL2_PCFGQOS1_0, 0x003f003f},
	{uMCTL2_PCFGWQOS0_0, 0x01100a08},
	{uMCTL2_PCFGWQOS1_0, 0x003f003f},
	{uMCTL2_PCFGR_1, 0x707f},
	{uMCTL2_PCFGW_1, 0x707f},
	{uMCTL2_PCFGQOS0_1, 0x02200a08},
	{uMCTL2_PCFGQOS1_1, 0x003f003f},
	{uMCTL2_PCFGWQOS0_1, 0x01100a08},
	{uMCTL2_PCFGWQOS1_1, 0x003f003f},
	{uMCTL2_PCFGR_2, 0x707f},
	{uMCTL2_PCFGW_2, 0x707f},
	{uMCTL2_PCFGQOS0_2, 0x02200a08},
	{uMCTL2_PCFGQOS1_2, 0x003f003f},
	{uMCTL2_PCFGWQOS0_2, 0x01100a08},
	{uMCTL2_PCFGWQOS1_2, 0x003f003f},
	{uMCTL2_PCFGR_3, 0x707f},
	{uMCTL2_PCFGW_3, 0x707f},
	{uMCTL2_PCFGQOS0_3, 0x02200a08},
	{uMCTL2_PCFGQOS1_3, 0x003f003f},
	{uMCTL2_PCFGWQOS0_3, 0x01100a08},
	{uMCTL2_PCFGWQOS1_3, 0x003f003f},
	{uMCTL2_PCFGR_4, 0x707f},
	{uMCTL2_PCFGW_4, 0x707f},
	{uMCTL2_PCFGQOS0_4, 0x02200a08},
	{uMCTL2_PCFGQOS1_4, 0x003f003f},
	{uMCTL2_PCFGWQOS0_4, 0x01100a08},
	{uMCTL2_PCFGWQOS1_4, 0x003f003f},
	{uMCTL2_PCFGR_5, 0x707f},
	{uMCTL2_PCFGW_5, 0x707f},
	{uMCTL2_PCFGQOS0_5, 0x02200a08},
	{uMCTL2_PCFGQOS1_5, 0x003f003f},
	{uMCTL2_PCFGWQOS0_5, 0x01100a08},
	{uMCTL2_PCFGWQOS1_5, 0x003f003f},
	{uMCTL2_PCFGR_6, 0x707f},
	{uMCTL2_PCFGW_6, 0x707f},
	{uMCTL2_PCFGQOS0_6, 0x02200a08},
	{uMCTL2_PCFGQOS1_6, 0x003f003f},
	{uMCTL2_PCFGWQOS0_6, 0x01100a08},
	{uMCTL2_PCFGWQOS1_6, 0x003f003f},
	{uMCTL2_PCFGR_7, 0x707f},
	{uMCTL2_PCFGW_7, 0x707f},
	{uMCTL2_PCFGQOS0_7, 0x02200a08},
	{uMCTL2_PCFGQOS1_7, 0x003f003f},
	{uMCTL2_PCFGWQOS0_7, 0x01100a08},
	{uMCTL2_PCFGWQOS1_7, 0x003f003f},
	{uMCTL2_SBRCTL, 0x3f00},
	{uMCTL2_SBRWDATA0, 0x4aa46fcc},
	{uMCTL2_SBRSTART0, 0x108c3f12},
	{uMCTL2_SBRSTART1, 0x0},
	{uMCTL2_SBRRANGE0, 0x108c46ff},
	{uMCTL2_SBRRANGE1, 0x0},
	{uMCTL2_FREQ1_DERATEEN, 0x1404},
	{uMCTL2_FREQ1_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ1_PWRTMG, 0x60b01},
	{uMCTL2_FREQ1_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ1_RFSHTMG, 0x82012c},
	{uMCTL2_FREQ1_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ1_INIT3, 0x74003f},
	{uMCTL2_FREQ1_INIT4, 0xf30000},
	{uMCTL2_FREQ1_INIT6, 0x4004d},
	{uMCTL2_FREQ1_INIT7, 0x4d},
	{uMCTL2_FREQ1_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ1_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ1_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ1_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ1_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ1_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ1_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ1_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ1_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ1_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ1_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ1_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ1_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ1_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ1_DRAMTMG14, 0x134},
	{uMCTL2_FREQ1_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ1_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ1_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ1_DFITMG1, 0x90303},
	{uMCTL2_FREQ1_DFITMG2, 0x230e},
	{uMCTL2_FREQ1_DFITMG3, 0x1d},
	{uMCTL2_FREQ1_ODTCFG, 0xe0a0824},
	{uMCTL2_FREQ2_DERATEEN, 0x1404},
	{uMCTL2_FREQ2_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ2_PWRTMG, 0x60b01},
	{uMCTL2_FREQ2_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ2_RFSHTMG, 0x82812c},
	{uMCTL2_FREQ2_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ2_INIT3, 0x74003f},
	{uMCTL2_FREQ2_INIT4, 0xf30000},
	{uMCTL2_FREQ2_INIT6, 0x4004d},
	{uMCTL2_FREQ2_INIT7, 0x4d},
	{uMCTL2_FREQ2_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ2_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ2_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ2_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ2_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ2_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ2_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ2_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ2_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ2_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ2_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ2_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ2_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ2_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ2_DRAMTMG14, 0x134},
	{uMCTL2_FREQ2_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ2_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ2_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ2_DFITMG1, 0x90303},
	{uMCTL2_FREQ2_DFITMG2, 0x230e},
	{uMCTL2_FREQ2_DFITMG3, 0x1d},
	{uMCTL2_FREQ2_ODTCFG, 0xe0a0824},
	{uMCTL2_FREQ3_DERATEEN, 0x1404},
	{uMCTL2_FREQ3_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ3_PWRTMG, 0x60b01},
	{uMCTL2_FREQ3_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ3_RFSHTMG, 0x82812c},
	{uMCTL2_FREQ3_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ3_INIT3, 0x74003f},
	{uMCTL2_FREQ3_INIT4, 0xf30000},
	{uMCTL2_FREQ3_INIT6, 0x4004d},
	{uMCTL2_FREQ3_INIT7, 0x4d},
	{uMCTL2_FREQ3_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ3_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ3_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ3_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ3_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ3_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ3_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ3_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ3_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ3_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ3_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ3_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ3_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ3_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ3_DRAMTMG14, 0x134},
	{uMCTL2_FREQ3_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ3_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ3_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ3_DFITMG1, 0x90303},
	{uMCTL2_FREQ3_DFITMG2, 0x230e},
	{uMCTL2_FREQ3_DFITMG3, 0x1d},
	{uMCTL2_FREQ3_ODTCFG, 0xe0a0824},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller default setting customization here
	#endif
};

uint32_t get_sizeof_ddr4_ddrc_cfg(void)
{
	return ARRAY_SIZE(ddr4_ddrc_cfg);
}

//============================================== 3200 ==============================================//
/* Start to config, default 3200mbps */

struct DRAM_CFG_PARAM ddr4_3200_ddrc_cfg[] = {
#if defined(M_D4_8Gb_32_A0)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00C30118},
	{uMCTL2_DRAMTMG0, 0x1818361A},
	{uMCTL2_DRAMTMG1, 0x00050625},
	{uMCTL2_DRAMTMG2, 0x090B0612},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0B04060C},
	{uMCTL2_DRAMTMG5, 0x08080504},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x05051009},
	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x190B010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000186A0},
	{uMCTL2_DFITMG0, 0x0391820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x0000110D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x20500001},
	{uMCTL2_INIT4, 0x08300400},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100500},
	{uMCTL2_INIT7, 0x0000100A},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},
#elif defined(M_D4_8Gb_32_A1)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00C30118},
	{uMCTL2_DRAMTMG0, 0x1818361A},
	{uMCTL2_DRAMTMG1, 0x00050625},
	{uMCTL2_DRAMTMG2, 0x090B0612},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0B04060C},
	{uMCTL2_DRAMTMG5, 0x08080504},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x05051009},
	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x190B010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000186A0},
	{uMCTL2_DFITMG0, 0x0391820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x0000110D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x20500001},
	{uMCTL2_INIT4, 0x08300400},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x0000100A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#elif defined(M_D4_32_A2)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00C300D0},
	{uMCTL2_DRAMTMG0, 0x1818361A},
	{uMCTL2_DRAMTMG1, 0x00050625},
	{uMCTL2_DRAMTMG2, 0x090B0612},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0B04060C},
	{uMCTL2_DRAMTMG5, 0x08080504},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03031007},
	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x170B010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000186A0},
	{uMCTL2_DFITMG0, 0x0391820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x0000110D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x20500001},
	{uMCTL2_INIT4, 0x08300400},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x0000100A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#elif defined(M_D4_32_A2R)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x003000D0},
	{uMCTL2_DRAMTMG0, 0x18180D1A},
	{uMCTL2_DRAMTMG1, 0x00050625},
	{uMCTL2_DRAMTMG2, 0x090B0612},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0B04060C},
	{uMCTL2_DRAMTMG5, 0x08080504},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03031007},
	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x170B010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000186A0},
	{uMCTL2_DFITMG0, 0x0391820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x0000110D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x20500001},
	{uMCTL2_INIT4, 0x08300400},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x0000100A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#else
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00C300D0},
	{uMCTL2_DRAMTMG0, 0x1818361A},
	{uMCTL2_DRAMTMG1, 0x00050625},
	{uMCTL2_DRAMTMG2, 0x090B0612},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0B04060C},
	{uMCTL2_DRAMTMG5, 0x08080504},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03031007},
	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x170B010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000186A0},
	{uMCTL2_DFITMG0, 0x0391820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x0000110D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x20500001},
	{uMCTL2_INIT4, 0x08300400},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x0000100A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#if defined(S_D4_26_A3)
	/* update ddr4 performance */
	{uMCTL2_ADDRMAP0, 0x1f1f1f},
	{uMCTL2_ADDRMAP1, 0x3f0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_ADDRMAP5, 0x070f0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0xf0f},
	{uMCTL2_ADDRMAP8, 0x3f01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x1f1f07},

	{uMCTL2_DRAMTMG9, 0x4001050E},
	{uMCTL2_PCCFG, 0x001},
	{uMCTL2_RFSHCTL0, 0x210050},
#endif

	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller 3200 customization here
	#endif
#endif
};

uint32_t get_sizeof_ddr4_3200_ddrc_cfg(void)
{
	return ARRAY_SIZE(ddr4_3200_ddrc_cfg);
}

struct DRAM_CFG_PARAM ddr4_2666_ddrc_cfg_micron[] = {

#if defined(M_D4_26_A1)
/*
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200AE},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x08090510},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0904050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x4002040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038D820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000D0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000708},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E400001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
*/
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200AE},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x08090510},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0904050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x4001040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038D820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000D0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000708},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E400001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#elif defined(M_D4_26_A2)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200AE},
	{uMCTL2_DRAMTMG0, 0x13142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x0709050E},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0904050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x0002040B},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038D8209},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000D09},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0A400001},
	{uMCTL2_INIT4, 0x08200200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x08100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#elif defined(M_D4_26_A3)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200AE},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x08090510},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0904050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x4002040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038D820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000D0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000708},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E400001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x10100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F1717},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x040F0404},
	{uMCTL2_ADDRMAP6, 0x0F040404},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F19},
	{uMCTL2_ADDRMAP9, 0x04040404},
	{uMCTL2_ADDRMAP10, 0x04040404},
	{uMCTL2_ADDRMAP11, 0x001F1F04},
#elif defined(M_D4_26_A0)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200AE},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x080A0510},
	{uMCTL2_DRAMTMG3, 0x0000500C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x4001040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038E820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x0700070C},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E700001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#elif defined(M_D4_8Gb_26_A0)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x00040520},
	{uMCTL2_DRAMTMG2, 0x080A0610},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050B},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG9, 0x4001040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038F820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000F0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000710},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E440001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#elif defined(M_D4_8Gb_26_A1)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x14142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x080A0510},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG9, 0x4001040D},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038E820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x0700070C},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E700001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},

	{uMCTL2_DBICTL, 0x00000001},

#else
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0xa200ae},
	{uMCTL2_DRAMTMG0, 0x15142d15},
	{uMCTL2_DRAMTMG1, 0x40520},
	{uMCTL2_DRAMTMG2, 0x080a0610},
	{uMCTL2_DRAMTMG3, 0x400c},
	{uMCTL2_DRAMTMG4, 0x0a04050b},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG8, 0x4040e08},
	{uMCTL2_DRAMTMG9, 0x4002040d},
	{uMCTL2_DRAMTMG10, 0xe0c05},
	{uMCTL2_DRAMTMG11, 0x1509010e},
	{uMCTL2_DRAMTMG12, 0x8},
	{uMCTL2_ZQCTL0, 0x51000040},
	{uMCTL2_ZQCTL1, 0x00000070},
	{uMCTL2_DFITMG0, 0x038f820b},
	{uMCTL2_DFITMG1, 0xa0202},
	{uMCTL2_DFILPCFG0, 0x3c0b020},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x4f005d},
	{uMCTL2_DFITMG2, 0xf0b},
	{uMCTL2_ADDRMAP6, 0xf070707},
	{uMCTL2_DFIPHYMSTR, 0x0},
	{uMCTL2_ODTCFG, 0x7000710},
	{uMCTL2_ODTMAP, 0x11},
#endif

	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller 2666 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2666_ddrc_cfg_micron(void)
{
	return ARRAY_SIZE(ddr4_2666_ddrc_cfg_micron);
}

struct DRAM_CFG_PARAM ddr4_2640_ddrc_cfg_samsung[] = {
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A000AC},
	{uMCTL2_DRAMTMG0, 0x16142C16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0411},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030E06},
	{uMCTL2_DRAMTMG9, 0x4001040E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014244},
	{uMCTL2_DFITMG0, 0x038E820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00810000},
	{uMCTL2_INIT3, 0x0E700001},
	{uMCTL2_INIT4, 0x08300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},
	{uMCTL2_DBICTL, 0x00000001},
};

uint32_t get_sizeof_ddr4_2640_ddrc_cfg_samsung(void)
{
	return ARRAY_SIZE(ddr4_2640_ddrc_cfg_samsung);
}

struct DRAM_CFG_PARAM ddr4_2666_ddrc_cfg_samsung[] = {

#if defined(S_D4_26_A0)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x15142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0411},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG9, 0x4002040E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038E820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E700301},
	{uMCTL2_INIT4, 0x02300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100400},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#elif ( defined(S_D4_26_A1) || defined(S_D4_26_A2) )
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x15142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0511},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG9, 0x4002040E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038F820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000F0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000708},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E440301},
	{uMCTL2_INIT4, 0x02300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100400},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#elif defined(S_D4_26_A3)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x15142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0411},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038E820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E700301},
	{uMCTL2_INIT4, 0x02300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100400},
	{uMCTL2_INIT7, 0x00000C0A},

	/* update ddr4 performance */
	//{uMCTL2_ADDRMAP0, 0x1f1f17},
	{uMCTL2_ADDRMAP0, 0x1f1f1f},
	{uMCTL2_ADDRMAP1, 0x3f0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_ADDRMAP5, 0x070f0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0xf0f},
	{uMCTL2_ADDRMAP8, 0x3f01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x1f1f07},
	{uMCTL2_DRAMTMG9, 0x4001040E},
	{uMCTL2_PCCFG, 0x001},
	{uMCTL2_RFSHCTL0, 0x210050},
#elif defined(S_D4_26_A1R)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x005100EA},
	{uMCTL2_DRAMTMG0, 0x15141616},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0511},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG9, 0x4002040E},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038F820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000F0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000708},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E440301},
	{uMCTL2_INIT4, 0x08300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000400},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#else
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x00A200EA},
	{uMCTL2_DRAMTMG0, 0x15142D16},
	{uMCTL2_DRAMTMG1, 0x0004051F},
	{uMCTL2_DRAMTMG2, 0x090A0411},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x0A04050A},
	{uMCTL2_DRAMTMG5, 0x07070404},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040E08},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1509010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x00014571},
	{uMCTL2_DFITMG0, 0x038E820D},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000E0D},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x0E700301},
	{uMCTL2_INIT4, 0x02300200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100400},
	{uMCTL2_INIT7, 0x00000C0A},

	/* update ddr4 performance */
	{uMCTL2_ADDRMAP0, 0x1f1f1f},
	{uMCTL2_ADDRMAP1, 0x3f0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_ADDRMAP5, 0x070f0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0xf0f},
	{uMCTL2_ADDRMAP8, 0x3f01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x1f1f07},
	{uMCTL2_DRAMTMG9, 0x4001040E},
	{uMCTL2_PCCFG, 0x001},
	{uMCTL2_RFSHCTL0, 0x210050},
#endif

	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller 2666 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2666_ddrc_cfg_samsung(void)
{
	return ARRAY_SIZE(ddr4_2666_ddrc_cfg_samsung);
}

struct DRAM_CFG_PARAM ddr4_2400_ddrc_cfg[] = {
#if defined(S_D4_24_A0)
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x009200D2},
	{uMCTL2_DRAMTMG0, 0x14122814},
	{uMCTL2_DRAMTMG1, 0x0004051C},
	{uMCTL2_DRAMTMG2, 0x0809040F},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x09030409},
	{uMCTL2_DRAMTMG5, 0x06060403},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x04040C07},
	{uMCTL2_DRAMTMG9, 0x4002040C},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1309010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000124F8},
	{uMCTL2_DFITMG0, 0x038C820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000C0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00760000},
	{uMCTL2_INIT3, 0x0A640001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18100500},
	{uMCTL2_INIT7, 0x00000C0A},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F0A},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#else
	{uMCTL2_RFSHTMG, 0x92009d},
	{uMCTL2_INIT3, 0xa340201},//mr0
	{uMCTL2_INIT4, 0x08280200},//mr2/3
	{uMCTL2_INIT5, 0x110224},//zq init
	{uMCTL2_INIT6, 0x18000880},//mr4/5
	{uMCTL2_INIT7, 0x0818},//mr6
	{uMCTL2_DRAMTMG0, 0x14132813},
	{uMCTL2_DRAMTMG1, 0x4051b},//txp/tr2pre/trc
	//{uMCTL2_DRAMTMG2, 0x70a0610},//wl/cl/r2w/w2r
	{uMCTL2_DRAMTMG2, 0x0808040f},//wl/cl/r2w/w2r
	{uMCTL2_DRAMTMG3, 0x400c},// tmrd/tmod
	{uMCTL2_DRAMTMG4, 0x08030409},//trcd/ccd/rrd/rp
	{uMCTL2_DRAMTMG5, 0x07070404},//tcksrx/cksre/ckesr/cke
	{uMCTL2_DRAMTMG9, 0x4002040c},
	{uMCTL2_DRAMTMG10, 0x100d0a},
	{uMCTL2_DRAMTMG11, 0x1309011c},
	{uMCTL2_DRAMTMG12, 0x0c00000d},
	//{uMCTL2_ZQCTL0, 0xc1000040},
	{uMCTL2_ZQCTL0, 0x31000040},
	{uMCTL2_ZQCTL1, 0x00000070},
	{uMCTL2_DFITMG0, 0x048a8209},//[23]:HDR/SDR DFI/DFI PHY Clock
	{uMCTL2_DFITMG1, 0x0070303},
	{uMCTL2_DFILPCFG0, 0x3b05030},
	{uMCTL2_DFIUPD0, 0xc0400018},
	{uMCTL2_DFIUPD1, 0x14004d},
	{uMCTL2_DFITMG2, 0xa09},
	{uMCTL2_ODTCFG, 0x70d0718},
	{uMCTL2_ODTMAP, 0x1211},
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller 2400 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2400_ddrc_cfg(void)
{
	return ARRAY_SIZE(ddr4_2400_ddrc_cfg);
}

//for multi-file
struct DRAM_CFG_PARAM ddr4_2400_ddrc_cfg_D4S512M_S24_A3[] = {
	{uMCTL2_MSTR, 0x81040010},
	{uMCTL2_RFSHTMG, 0x0092009C},
	{uMCTL2_DRAMTMG0, 0x14122814},
	{uMCTL2_DRAMTMG1, 0x0004051C},
	{uMCTL2_DRAMTMG2, 0x0809040F},
	{uMCTL2_DRAMTMG3, 0x0000400C},
	{uMCTL2_DRAMTMG4, 0x09030409},
	{uMCTL2_DRAMTMG5, 0x06060403},
	{uMCTL2_DRAMTMG6, 0x00000000},
	{uMCTL2_DRAMTMG7, 0x00000000},
	{uMCTL2_DRAMTMG8, 0x03030C06},
	{uMCTL2_DRAMTMG9, 0x4001040C},
	{uMCTL2_DRAMTMG10, 0x000E0C05},
	{uMCTL2_DRAMTMG11, 0x1209010E},
	{uMCTL2_DRAMTMG12, 0x0C000008},
	{uMCTL2_ZQCTL0, 0x01000040},
	{uMCTL2_ZQCTL1, 0x000124F8},
	{uMCTL2_DFITMG0, 0x038C820B},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03C0B040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x004F005D},
	{uMCTL2_DFITMG2, 0x00000C0B},
	{uMCTL2_DFIPHYMSTR, 0x00000000},
	{uMCTL2_ODTCFG, 0x07000704},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020002},
	{uMCTL2_INIT1, 0x00760000},
	{uMCTL2_INIT3, 0x0A640001},
	{uMCTL2_INIT4, 0x08280200},
	{uMCTL2_INIT5, 0x00110000},
	{uMCTL2_INIT6, 0x18000500},
	{uMCTL2_INIT7, 0x0000080A},
	{uMCTL2_RFSHCTL0, 0x00210050},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x003F0909},
	{uMCTL2_ADDRMAP2, 0x00000700},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F01},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_PCCFG, 0x00000001},
	{uMCTL2_DBICTL, 0x00000001},
};

struct DRAM_CFG_PARAM ddr4_1600_ddrc_cfg[] = {
	{uMCTL2_MSTR, 0x83040210},
	{uMCTL2_MRCTRL0, 0x40001030},
	{uMCTL2_MRCTRL1, 0xc502},
	{uMCTL2_MRCTRL2, 0x7cd207f1},
	{uMCTL2_DERATEEN, 0x500},
	{uMCTL2_DERATEINT, 0x3f53492},
	{uMCTL2_PWRTMG, 0x40cf04},
	{uMCTL2_HWLPCTL, 0x580002},
	{uMCTL2_RFSHCTL1, 0x46000a},
	{uMCTL2_RFSHTMG, 0x6180dc},
	{uMCTL2_INIT2, 0xa90a},
	{uMCTL2_INIT3, 0x2150201},
	{uMCTL2_INIT4, 0x100400},
	{uMCTL2_INIT5, 0x1100ad},
	{uMCTL2_INIT7, 0x418},
	{uMCTL2_DRAMTMG0, 0xe0e1a0e},//
	{uMCTL2_DRAMTMG1, 0x30214},//
	{uMCTL2_DRAMTMG2, 0x606040b},//
	{uMCTL2_DRAMTMG3, 0x400c},//
	{uMCTL2_DRAMTMG4, 0x6030307},//
	{uMCTL2_DRAMTMG5, 0x4040302},
	{uMCTL2_DRAMTMG7, 0x404},
	{uMCTL2_DRAMTMG8, 0x5050b09},
	{uMCTL2_DRAMTMG9, 0x20309},//
	{uMCTL2_DRAMTMG10, 0x100c0b},
	{uMCTL2_DRAMTMG11, 0x12060117},
	{uMCTL2_DRAMTMG12, 0xc000008},
	{uMCTL2_ZQCTL0, 0xf1000040},
	{uMCTL2_ZQCTL1, 0x26a8f},
	{uMCTL2_DFITMG0, 0x3878206},//
	{uMCTL2_DFITMG1, 0x3090303},//
	{uMCTL2_DFILPCFG0, 0x3105100},
	{uMCTL2_DFILPCFG1, 0x20},
	{uMCTL2_DFIUPD0, 0xc0400018},
	{uMCTL2_DFIUPD1, 0x2f00f4},
	{uMCTL2_DFITMG2, 0x706},//
	{uMCTL2_ODTCFG, 0x6030618},
	{uMCTL2_ODTMAP, 0x1220},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 controller 1600 customization here
	#endif
};

uint32_t get_sizeof_ddr4_1600_ddrc_cfg(void)
{
	return ARRAY_SIZE(ddr4_1600_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_ddrc_cfg[] = {
#if (CVB_M_ENABLE == 1)
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x82080096},
	{uMCTL2_DRAMTMG0, 0x2121242D},
	{uMCTL2_DRAMTMG1, 0x00090941},
	{uMCTL2_DRAMTMG2, 0x09121519},
	{uMCTL2_DRAMTMG3, 0x00F0F000},
	{uMCTL2_DRAMTMG4, 0x14040914},
	{uMCTL2_DRAMTMG5, 0x02061111},
	{uMCTL2_DRAMTMG6, 0x0000000A},
	{uMCTL2_DRAMTMG7, 0x00000602},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0E100002},
	{uMCTL2_DRAMTMG14, 0x00000133},
	{uMCTL2_ZQCTL0, 0xC42B0021},
	{uMCTL2_ZQCTL1, 0x03648BD4},
	{uMCTL2_DFITMG0, 0x049F820E},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001F0E},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC0030824},
	{uMCTL2_INIT1, 0x00D10000},
	{uMCTL2_INIT3, 0x0074003F},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00610000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#else
	/* Start to config, default 4266mbps */
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_MRCTRL0, 0x40007010},
	{uMCTL2_MRCTRL1, 0x1a6e7},
	{uMCTL2_MRCTRL2, 0xa37f33dd},
	{uMCTL2_DERATEEN, 0x1404},
	{uMCTL2_DERATEINT, 0xe444a1f3},
	{uMCTL2_MSTR2, 0x0},
	{uMCTL2_DERATECTL, 0x0},
	{uMCTL2_PWRCTL, 0x0},
	{uMCTL2_PWRTMG, 0x404704},
	{uMCTL2_HWLPCTL, 0xa30000},
	{uMCTL2_RFSHCTL0, 0x210004},
	//{uMCTL2_RFSHCTL3, 0x1},
	{uMCTL2_RFSHTMG, RFSHTMG_LPDDR4_MICRON},
	{uMCTL2_RFSHTMG1, RFSHTMG1_LPDDR4_MICRON},
	{uMCTL2_ECCCFG0, 0x33f7f10},
	{uMCTL2_ECCCFG1, 0x790},
	{uMCTL2_ECCCTL, 0x700},
	{uMCTL2_ECCPOISONADDR0, 0x0},
	{uMCTL2_ECCPOISONADDR1, 0x0},
	{uMCTL2_CRCPARCTL0, 0x0},
	{uMCTL2_CRCPARCTL1, 0x0},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x30002},
	{uMCTL2_INIT2, 0x5105},
	{uMCTL2_INIT3, 0x74003f},
	{uMCTL2_INIT4, 0x320000},
	{uMCTL2_INIT5, 0x5000c},
	{uMCTL2_INIT6, 0x4d},
	{uMCTL2_INIT7, 0x4d},
	{uMCTL2_DIMMCTL, 0x0},
	{uMCTL2_RANKCTL, 0xfbe2},
	{uMCTL2_DRAMTMG0, 0x2121482d},
	{uMCTL2_DRAMTMG1, 0x90901},
	{uMCTL2_DRAMTMG2, DRAMTMG2_LPDDR4_MICRON},
	{uMCTL2_DRAMTMG3, 0xf0f006},
	{uMCTL2_DRAMTMG4, 0x14040914},
	{uMCTL2_DRAMTMG5, 0x2061111},
	{uMCTL2_DRAMTMG6, 0x101000a},
	{uMCTL2_DRAMTMG7, 0x602},
	{uMCTL2_DRAMTMG8, 0x1010101},
	{uMCTL2_DRAMTMG9, 0x5},
	{uMCTL2_DRAMTMG10, 0x40904},
	{uMCTL2_DRAMTMG11, 0x101001f},
	{uMCTL2_DRAMTMG12, 0x20000},
	{uMCTL2_DRAMTMG13, 0xe100002},
	{uMCTL2_DRAMTMG14, 0x134},
	{uMCTL2_DRAMTMG15, 0x80000000},
	{uMCTL2_ZQCTL0, 0xc42f0021},
	{uMCTL2_ZQCTL1, 0x3648e2a},
	{uMCTL2_ZQCTL2, 0x0},
	{uMCTL2_DFITMG0, 0x49f820e},
	{uMCTL2_DFITMG1, 0xc0303},
	{uMCTL2_DFILPCFG0, 0x3807100},
	{uMCTL2_DFILPCFG1, 0x61},
	{uMCTL2_DFIUPD0, 0xa0400018},
	{uMCTL2_DFIUPD1, 0xc200cb},
	{uMCTL2_DFIUPD2, 0x0},
	{uMCTL2_DFIMISC, 0x41},
	{uMCTL2_DFITMG2, 0x1f0e},
	{uMCTL2_DFITMG3, 0x8},
	{uMCTL2_DBICTL, 0x1},
#ifdef CONFIG_SUPPORT_PALLADIUM
	{uMCTL2_DFIPHYMSTR, 0x0},
#else
	{uMCTL2_DFIPHYMSTR, 0x1},
#endif
	{uMCTL2_ADDRMAP0, 0x17},
	{uMCTL2_ADDRMAP1, 0x80808},
	{uMCTL2_ADDRMAP2, 0x0},
	{uMCTL2_ADDRMAP3, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_ADDRMAP5, 0x70f0707},
	{uMCTL2_ADDRMAP6, 0x7070707},
	{uMCTL2_ADDRMAP7, 0xf0f},
	{uMCTL2_ADDRMAP8, 0x3f3f},
	{uMCTL2_ADDRMAP9, 0x7070707},
	{uMCTL2_ADDRMAP10, 0x7070707},
	{uMCTL2_ADDRMAP11, 0x7},
	{uMCTL2_ODTCFG, 0x60a0c28},
	{uMCTL2_ODTMAP, 0x0},
	{uMCTL2_SCHED, 0x20003601},
	{uMCTL2_SCHED1, 0x0},
	{uMCTL2_PERFHPR1, 0xf000001},
	{uMCTL2_PERFLPR1, 0xf00007f},
	{uMCTL2_PERFWR1, 0xf00007f},
	{uMCTL2_DBG0, 0x0},
	{uMCTL2_DBG1, 0x0},
	{uMCTL2_DBGCMD, 0x0},
	{uMCTL2_SWCTL, 0x1},
	{uMCTL2_SWCTLSTATIC, 0x0},
	{uMCTL2_POISONCFG, 0x110000},
	{uMCTL2_ADVECCINDEX, 0x171},
	{uMCTL2_ECCPOISONPAT0, 0x0},
	{uMCTL2_ECCPOISONPAT2, 0x0},
	{uMCTL2_PCCFG, 0x0},
	{uMCTL2_PCFGR_0, 0x707f},
	{uMCTL2_PCFGW_0, 0x707f},
	{uMCTL2_PCFGQOS0_0, 0x02200a08},
	{uMCTL2_PCFGQOS1_0, 0x003f003f},
	{uMCTL2_PCFGWQOS0_0, 0x01100a08},
	{uMCTL2_PCFGWQOS1_0, 0x003f003f},
	{uMCTL2_PCFGR_1, 0x707f},
	{uMCTL2_PCFGW_1, 0x707f},
	{uMCTL2_PCFGQOS0_1, 0x02200a08},
	{uMCTL2_PCFGQOS1_1, 0x003f003f},
	{uMCTL2_PCFGWQOS0_1, 0x01100a08},
	{uMCTL2_PCFGWQOS1_1, 0x003f003f},
	{uMCTL2_PCFGR_2, 0x707f},
	{uMCTL2_PCFGW_2, 0x707f},
	{uMCTL2_PCFGQOS0_2, 0x02200a08},
	{uMCTL2_PCFGQOS1_2, 0x003f003f},
	{uMCTL2_PCFGWQOS0_2, 0x01100a08},
	{uMCTL2_PCFGWQOS1_2, 0x003f003f},
	{uMCTL2_PCFGR_3, 0x707f},
	{uMCTL2_PCFGW_3, 0x707f},
	{uMCTL2_PCFGQOS0_3, 0x02200a08},
	{uMCTL2_PCFGQOS1_3, 0x003f003f},
	{uMCTL2_PCFGWQOS0_3, 0x01100a08},
	{uMCTL2_PCFGWQOS1_3, 0x003f003f},
	{uMCTL2_PCFGR_4, 0x707f},
	{uMCTL2_PCFGW_4, 0x707f},
	{uMCTL2_PCFGQOS0_4, 0x02200a08},
	{uMCTL2_PCFGQOS1_4, 0x003f003f},
	{uMCTL2_PCFGWQOS0_4, 0x01100a08},
	{uMCTL2_PCFGWQOS1_4, 0x003f003f},
	{uMCTL2_PCFGR_5, 0x707f},
	{uMCTL2_PCFGW_5, 0x707f},
	{uMCTL2_PCFGQOS0_5, 0x02200a08},
	{uMCTL2_PCFGQOS1_5, 0x003f003f},
	{uMCTL2_PCFGWQOS0_5, 0x01100a08},
	{uMCTL2_PCFGWQOS1_5, 0x003f003f},
	{uMCTL2_PCFGR_6, 0x707f},
	{uMCTL2_PCFGW_6, 0x707f},
	{uMCTL2_PCFGQOS0_6, 0x02200a08},
	{uMCTL2_PCFGQOS1_6, 0x003f003f},
	{uMCTL2_PCFGWQOS0_6, 0x01100a08},
	{uMCTL2_PCFGWQOS1_6, 0x003f003f},
	{uMCTL2_PCFGR_7, 0x707f},
	{uMCTL2_PCFGW_7, 0x707f},
	{uMCTL2_PCFGQOS0_7, 0x02200a08},
	{uMCTL2_PCFGQOS1_7, 0x003f003f},
	{uMCTL2_PCFGWQOS0_7, 0x01100a08},
	{uMCTL2_PCFGWQOS1_7, 0x003f003f},
	{uMCTL2_SBRCTL, 0x3f40},
	{uMCTL2_SBRWDATA0, 0x4aa46fcc},
	{uMCTL2_SBRSTART0, 0x108c3f12},
	{uMCTL2_SBRSTART1, 0x0},
	{uMCTL2_SBRRANGE0, 0x108c46ff},
	{uMCTL2_SBRRANGE1, 0x0},
	{uMCTL2_FREQ1_DERATEEN, 0x1404},
	{uMCTL2_FREQ1_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ1_PWRTMG, 0x60b01},
	{uMCTL2_FREQ1_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ1_RFSHTMG, 0x82012c},
	{uMCTL2_FREQ1_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ1_INIT3, 0x74003f},
	{uMCTL2_FREQ1_INIT4, 0xf30000},
	{uMCTL2_FREQ1_INIT6, 0x4004d},
	{uMCTL2_FREQ1_INIT7, 0x4d},
	{uMCTL2_FREQ1_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ1_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ1_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ1_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ1_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ1_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ1_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ1_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ1_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ1_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ1_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ1_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ1_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ1_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ1_DRAMTMG14, 0x134},
	{uMCTL2_FREQ1_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ1_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ1_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ1_DFITMG1, 0x90303},
	{uMCTL2_FREQ1_DFITMG2, 0x230e},
	{uMCTL2_FREQ1_DFITMG3, 0x1d},
	{uMCTL2_FREQ1_ODTCFG, 0xe0a0824},
	{uMCTL2_FREQ2_DERATEEN, 0x1404},
	{uMCTL2_FREQ2_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ2_PWRTMG, 0x60b01},
	{uMCTL2_FREQ2_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ2_RFSHTMG, 0x82812c},
	{uMCTL2_FREQ2_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ2_INIT3, 0x74003f},
	{uMCTL2_FREQ2_INIT4, 0xf30000},
	{uMCTL2_FREQ2_INIT6, 0x4004d},
	{uMCTL2_FREQ2_INIT7, 0x4d},
	{uMCTL2_FREQ2_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ2_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ2_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ2_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ2_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ2_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ2_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ2_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ2_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ2_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ2_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ2_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ2_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ2_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ2_DRAMTMG14, 0x134},
	{uMCTL2_FREQ2_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ2_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ2_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ2_DFITMG1, 0x90303},
	{uMCTL2_FREQ2_DFITMG2, 0x230e},
	{uMCTL2_FREQ2_DFITMG3, 0x1d},
	{uMCTL2_FREQ2_ODTCFG, 0xe0a0824},
	{uMCTL2_FREQ3_DERATEEN, 0x1404},
	{uMCTL2_FREQ3_DERATEINT, 0xe4de67fb},
	{uMCTL2_FREQ3_PWRTMG, 0x60b01},
	{uMCTL2_FREQ3_RFSHCTL0, 0xc1f030},
	{uMCTL2_FREQ3_RFSHTMG, 0x82812c},
	{uMCTL2_FREQ3_RFSHTMG1, 0x610000},
	{uMCTL2_FREQ3_INIT3, 0x74003f},
	{uMCTL2_FREQ3_INIT4, 0xf30000},
	{uMCTL2_FREQ3_INIT6, 0x4004d},
	{uMCTL2_FREQ3_INIT7, 0x4d},
	{uMCTL2_FREQ3_DRAMTMG0, 0x2121482d},
	{uMCTL2_FREQ3_DRAMTMG1, 0x90901},
	{uMCTL2_FREQ3_DRAMTMG2, 0x9141c1d},
	{uMCTL2_FREQ3_DRAMTMG3, 0xf0f006},
	{uMCTL2_FREQ3_DRAMTMG4, 0x14040914},
	{uMCTL2_FREQ3_DRAMTMG5, 0xf0c1111},
	{uMCTL2_FREQ3_DRAMTMG6, 0x204000f},
	{uMCTL2_FREQ3_DRAMTMG7, 0xf07},
	{uMCTL2_FREQ3_DRAMTMG8, 0x1012801},
	{uMCTL2_FREQ3_DRAMTMG9, 0x4000003b},
	{uMCTL2_FREQ3_DRAMTMG10, 0xd0400},
	{uMCTL2_FREQ3_DRAMTMG11, 0x101000d},
	{uMCTL2_FREQ3_DRAMTMG12, 0x20000},
	{uMCTL2_FREQ3_DRAMTMG13, 0xe100002},
	{uMCTL2_FREQ3_DRAMTMG14, 0x134},
	{uMCTL2_FREQ3_DRAMTMG15, 0x80000000},
	{uMCTL2_FREQ3_ZQCTL0, 0x542f0021},
	{uMCTL2_FREQ3_DFITMG0, 0x4a3820e},
	{uMCTL2_FREQ3_DFITMG1, 0x90303},
	{uMCTL2_FREQ3_DFITMG2, 0x230e},
	{uMCTL2_FREQ3_DFITMG3, 0x1d},
	{uMCTL2_FREQ3_ODTCFG, 0xe0a0824},
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller default setting customization here
	#endif
};

uint32_t get_sizeof_lpddr4_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_ddrc_cfg);
}

#define LPDDR4_DDRC_FREQS_CFG_P1_2666 \
	{uMCTL2_FREQ1_RFSHTMG, 0x8145003C}, \
	{uMCTL2_FREQ1_DRAMTMG0, 0x171B161C}, \
	{uMCTL2_FREQ1_DRAMTMG1, 0x00050528}, \
	{uMCTL2_FREQ1_DRAMTMG2, 0x060C1112}, \
	{uMCTL2_FREQ1_DRAMTMG3, 0x00A0A000}, \
	{uMCTL2_FREQ1_DRAMTMG4, 0x0C04070D}, \
	{uMCTL2_FREQ1_DRAMTMG5, 0x02040A0A}, \
	{uMCTL2_FREQ1_DRAMTMG6, 0x00000006}, \
	{uMCTL2_FREQ1_DRAMTMG7, 0x00000402}, \
	{uMCTL2_FREQ1_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ1_DRAMTMG13, 0x0B100002}, \
	{uMCTL2_FREQ1_DRAMTMG14, 0x0000007D}, \
	{uMCTL2_FREQ1_ZQCTL0, 0xC29B0014}, \
	{uMCTL2_FREQ1_DFITMG0, 0x03938208},/*Janice 2*/ \
	{uMCTL2_FREQ1_DFITMG1, 0x000D0202}, \
	{uMCTL2_FREQ1_DFITMG2, 0x00001308}, \
	{uMCTL2_FREQ1_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ1_INIT3, 0x00440024}, \
	{uMCTL2_FREQ1_INIT4, 0x00A30020}, \
	{uMCTL2_FREQ1_INIT6, 0x0066004C}, \
	{uMCTL2_FREQ1_INIT7, 0x0006004C}, \
	{uMCTL2_FREQ1_RFSHTMG1, 0x003C0000}, \
	{uMCTL2_FREQ1_RFSHCTL0, 0x00210004}, \
	{uMCTL2_FREQ1_DERATEEN, 0x00001203}, \
	{uMCTL2_FREQ1_DERATEINT, 0x6a25be4}, /*PC*/ \
	{uMCTL2_FREQ1_PWRTMG, 0x40fe10}, \
	{uMCTL2_FREQ1_RANKCTL, 0xf460}

#define LPDDR4_DDRC_FREQS_CFG_P1_1333 \
	{uMCTL2_FREQ1_RFSHTMG, 0x80A2001E}, \
	{uMCTL2_FREQ1_DRAMTMG0, 0x110E0A0E}, \
	{uMCTL2_FREQ1_DRAMTMG1, 0x00030414}, \
	{uMCTL2_FREQ1_DRAMTMG2, 0x04070D0D}, \
	{uMCTL2_FREQ1_DRAMTMG3, 0x00505000}, \
	{uMCTL2_FREQ1_DRAMTMG4, 0x06040407}, \
	{uMCTL2_FREQ1_DRAMTMG5, 0x02030505}, \
	{uMCTL2_FREQ1_DRAMTMG6, 0x00000004}, \
	{uMCTL2_FREQ1_DRAMTMG7, 0x00000302}, \
	{uMCTL2_FREQ1_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ1_DRAMTMG13, 0x00100002}, \
	{uMCTL2_FREQ1_DRAMTMG14, 0x0000003F}, \
	{uMCTL2_FREQ1_ZQCTL0, 0x814E000A}, \
	{uMCTL2_FREQ1_DFITMG0, 0x04898204}, \
	{uMCTL2_FREQ1_DFITMG1, 0x000D0303}, \
	{uMCTL2_FREQ1_DFITMG2, 0x00000904}, \
	{uMCTL2_FREQ1_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ1_INIT3, 0x00240012}, \
	{uMCTL2_FREQ1_INIT4, 0x00B30020}, \
	{uMCTL2_FREQ1_INIT6, 0x00430054}, \
	{uMCTL2_FREQ1_INIT7, 0x0014005C}, \
	{uMCTL2_FREQ1_RFSHTMG1, 0x001E0000}, \
	{uMCTL2_FREQ1_RFSHCTL0, 0x00210004}, \
	{uMCTL2_FREQ1_DERATEEN, 0x00001121}, \
	{uMCTL2_FREQ1_DERATEINT, 0x351318E}

#define LPDDR4_DDRC_FREQS_CFG_P1_1333_2G \
	{uMCTL2_FREQ1_RFSHTMG, 0x0028005E}, \
	{uMCTL2_FREQ1_DRAMTMG0, 0x120E0A0E}, \
	{uMCTL2_FREQ1_DRAMTMG1, 0x00030415}, \
	{uMCTL2_FREQ1_DRAMTMG2, 0x070E1410}, \
	{uMCTL2_FREQ1_DRAMTMG3, 0x00505000}, \
	{uMCTL2_FREQ1_DRAMTMG4, 0x06040408}, \
	{uMCTL2_FREQ1_DRAMTMG5, 0x02030505}, \
	{uMCTL2_FREQ1_DRAMTMG6, 0x00000004}, \
	{uMCTL2_FREQ1_DRAMTMG7, 0x00000302}, \
	{uMCTL2_FREQ1_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ1_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ1_DRAMTMG13, 0x00100002}, \
	{uMCTL2_FREQ1_DRAMTMG14, 0x00000060}, \
	{uMCTL2_FREQ1_ZQCTL0, 0x814E000A}, \
	{uMCTL2_FREQ1_DFITMG0, 0x04898204}, \
	{uMCTL2_FREQ1_DFITMG1, 0x000D0303}, \
	{uMCTL2_FREQ1_DFITMG2, 0x0000170A}, \
	{uMCTL2_FREQ1_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ1_INIT3, 0x0024002D}, \
	{uMCTL2_FREQ1_INIT4, 0x00B30020}, \
	{uMCTL2_FREQ1_INIT6, 0x00430054}, \
	{uMCTL2_FREQ1_INIT7, 0x0014005C}, \
	{uMCTL2_FREQ1_RFSHTMG1, 0x001E0000}, \
	{uMCTL2_FREQ1_RFSHCTL0, 0x00210000}, \
	{uMCTL2_FREQ1_DERATEEN, 0x00001121}, \
	{uMCTL2_FREQ1_DERATEINT, 0x351318E}

#define LPDDR4_DDRC_FREQS_CFG_P2_667 \
	{uMCTL2_FREQ2_DERATEINT, 0x1a84757}, \
	{uMCTL2_FREQ2_PWRTMG, 0x40fe10}, \
	{uMCTL2_FREQ2_RANKCTL, 0xf460}, \
	{uMCTL2_FREQ2_RFSHTMG, 0x80510010}, \
	{uMCTL2_FREQ2_DRAMTMG0, 0x0B070508}, \
	{uMCTL2_FREQ2_DRAMTMG1, 0x0003040B}, \
	{uMCTL2_FREQ2_DRAMTMG2, 0x03050B0C}, \
	{uMCTL2_FREQ2_DRAMTMG3, 0x00505000}, \
	{uMCTL2_FREQ2_DRAMTMG4, 0x04040204}, \
	{uMCTL2_FREQ2_DRAMTMG5, 0x02030303}, \
	{uMCTL2_FREQ2_DRAMTMG6, 0x00000004}, \
	{uMCTL2_FREQ2_DRAMTMG7, 0x00000302}, \
	{uMCTL2_FREQ2_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ2_DRAMTMG13, 0x00100002}, \
	{uMCTL2_FREQ2_DRAMTMG14, 0x00000020}, \
	{uMCTL2_FREQ2_ZQCTL0, 0xC0A70006}, \
	{uMCTL2_FREQ2_DFITMG2, 0x00000502}, \
	{uMCTL2_FREQ2_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ2_INIT3, 0x00140009}, \
	{uMCTL2_FREQ2_INIT4, 0x00B30000}, \
	{uMCTL2_FREQ2_INIT6, 0x00430054}, \
	{uMCTL2_FREQ2_INIT7, 0x0014005C}, \
	{uMCTL2_FREQ2_RFSHTMG1, 0x00100000}, \
	{uMCTL2_FREQ2_RFSHCTL0, 0x00210004}, \
	{uMCTL2_FREQ2_DERATEEN, 0x00001001}, \
	{uMCTL2_FREQ2_DFITMG0, 0x03858202}, \
	{uMCTL2_FREQ2_DFITMG1, 0x000D0202}

#define LPDDR4_DDRC_FREQS_CFG_P2_333 \
	{uMCTL2_FREQ2_DERATEINT, 0xD4239E}, \
	{uMCTL2_FREQ2_PWRTMG, 0x40fe10}, \
	{uMCTL2_FREQ2_RANKCTL, 0xf460}, \
	{uMCTL2_FREQ2_RFSHTMG, 0x80280008}, \
	{uMCTL2_FREQ2_DRAMTMG0, 0x0A040204}, \
	{uMCTL2_FREQ2_DRAMTMG1, 0x00030405}, \
	{uMCTL2_FREQ2_DRAMTMG2, 0x0203080B}, \
	{uMCTL2_FREQ2_DRAMTMG3, 0x00505000}, \
	{uMCTL2_FREQ2_DRAMTMG4, 0x02040202}, \
	{uMCTL2_FREQ2_DRAMTMG5, 0x02030202}, \
	{uMCTL2_FREQ2_DRAMTMG6, 0x00000004}, \
	{uMCTL2_FREQ2_DRAMTMG7, 0x00000302}, \
	{uMCTL2_FREQ2_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ2_DRAMTMG13, 0x00100002}, \
	{uMCTL2_FREQ2_DRAMTMG14, 0x00000010}, \
	{uMCTL2_FREQ2_ZQCTL0, 0x80540004}, \
	{uMCTL2_FREQ2_DFITMG0, 0x03818200}, \
	{uMCTL2_FREQ2_DFITMG1, 0x000D0202}, \
	{uMCTL2_FREQ2_DFITMG2, 0x00000100}, \
	{uMCTL2_FREQ2_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ2_INIT3, 0x00040000}, \
	{uMCTL2_FREQ2_INIT4, 0x00B30000}, \
	{uMCTL2_FREQ2_INIT6, 0x00430054}, \
	{uMCTL2_FREQ2_INIT7, 0x0014005C}, \
	{uMCTL2_FREQ2_RFSHTMG1, 0x00080000}, \
	{uMCTL2_FREQ2_RFSHCTL0, 0x00110004}, \
	{uMCTL2_FREQ2_DERATEEN, 0x00001021}

#define LPDDR4_DDRC_FREQS_CFG_P2_333_2G \
	{uMCTL2_FREQ2_DERATEINT, 0xD4239E}, \
	{uMCTL2_FREQ2_PWRTMG, 0x40fe10}, \
	{uMCTL2_FREQ2_RANKCTL, 0xf460}, \
	{uMCTL2_FREQ2_RFSHTMG, 0x000A0018}, \
	{uMCTL2_FREQ2_DRAMTMG0, 0x0A040204}, \
	{uMCTL2_FREQ2_DRAMTMG1, 0x00030406}, \
	{uMCTL2_FREQ2_DRAMTMG2, 0x0203080B}, \
	{uMCTL2_FREQ2_DRAMTMG3, 0x00505000}, \
	{uMCTL2_FREQ2_DRAMTMG4, 0x02040203}, \
	{uMCTL2_FREQ2_DRAMTMG5, 0x02030202}, \
	{uMCTL2_FREQ2_DRAMTMG6, 0x00000004}, \
	{uMCTL2_FREQ2_DRAMTMG7, 0x00000302}, \
	{uMCTL2_FREQ2_DRAMTMG8, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG9, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG10, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG11, 0x00000000}, \
	{uMCTL2_FREQ2_DRAMTMG12, 0x00020000}, \
	{uMCTL2_FREQ2_DRAMTMG13, 0x00100002}, \
	{uMCTL2_FREQ2_DRAMTMG14, 0x00000018}, \
	{uMCTL2_FREQ2_ZQCTL0, 0x80540004}, \
	{uMCTL2_FREQ2_DFITMG0, 0x03818200}, \
	{uMCTL2_FREQ2_DFITMG1, 0x000D0202}, \
	{uMCTL2_FREQ2_DFITMG2, 0x00000100}, \
	{uMCTL2_FREQ2_ODTCFG, 0x00000000}, \
	{uMCTL2_FREQ2_INIT3, 0x00040000}, \
	{uMCTL2_FREQ2_INIT4, 0x00B30000}, \
	{uMCTL2_FREQ2_INIT6, 0x00430054}, \
	{uMCTL2_FREQ2_INIT7, 0x0014005C}, \
	{uMCTL2_FREQ2_RFSHTMG1, 0x00080000}, \
	{uMCTL2_FREQ2_RFSHCTL0, 0x00210000}, \
	{uMCTL2_FREQ2_DERATEEN, 0x00001021}

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_2666_667_xg_1g[] = {
	//XS 2666
	LPDDR4_DDRC_FREQS_CFG_P1_2666,

	//XS 667
	LPDDR4_DDRC_FREQS_CFG_P2_667
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_2666_333_xg_1g[] = {
	//XS 2666
	LPDDR4_DDRC_FREQS_CFG_P1_2666,

	//XS 333
	{uMCTL2_FREQ2_DERATEINT, 0x7c215598},
	{uMCTL2_FREQ2_PWRTMG, 0x40fe10},
	{uMCTL2_FREQ2_RANKCTL, 0xf460},
	//{uMCTL2_FREQ2_RFSHTMG, 0x8028000c},
	{uMCTL2_FREQ2_RFSHTMG, 0x80280008},//Janice
	{uMCTL2_FREQ2_DRAMTMG0, 0x09040204},
	{uMCTL2_FREQ2_DRAMTMG1, 0x00030405},
	{uMCTL2_FREQ2_DRAMTMG2, 0x0203080B},
	{uMCTL2_FREQ2_DRAMTMG3, 0x00505000},
	{uMCTL2_FREQ2_DRAMTMG4, 0x02040202},
	{uMCTL2_FREQ2_DRAMTMG5, 0x02030202},
	{uMCTL2_FREQ2_DRAMTMG6, 0x00000004},
	{uMCTL2_FREQ2_DRAMTMG7, 0x00000302},
	{uMCTL2_FREQ2_DRAMTMG8, 0x00000000},
	{uMCTL2_FREQ2_DRAMTMG9, 0x00000000},
	{uMCTL2_FREQ2_DRAMTMG10, 0x00000000},
	{uMCTL2_FREQ2_DRAMTMG11, 0x00000000},
	{uMCTL2_FREQ2_DRAMTMG12, 0x00020000},
	{uMCTL2_FREQ2_DRAMTMG13, 0x00100002},
	//{uMCTL2_FREQ2_DRAMTMG14, 0x00000018},
	{uMCTL2_FREQ2_DRAMTMG14, 0x00000010},//Janice
	{uMCTL2_FREQ2_ZQCTL0, 0xC0540004},
	{uMCTL2_FREQ2_DFITMG0, 0x03818200},
	{uMCTL2_FREQ2_DFITMG1, 0x000D0202},
	{uMCTL2_FREQ2_DFITMG2, 0x00000100},
	{uMCTL2_FREQ2_ODTCFG, 0x00000000},
	{uMCTL2_FREQ2_INIT3, 0x00040000},
	{uMCTL2_FREQ2_INIT4, 0x00B30000},
	{uMCTL2_FREQ2_INIT6, 0x00430054},
	{uMCTL2_FREQ2_INIT7, 0x0014005C},
	{uMCTL2_FREQ2_RFSHTMG1, 0x00080000},
	{uMCTL2_FREQ2_RFSHCTL0, 0x00110004},
	//{uMCTL2_FREQ2_RFSHCTL0, 0x00210004}, //Janice
	{uMCTL2_FREQ2_DERATEEN, 0x00001001},
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_1333_667_xg_1g[] = {
        LPDDR4_DDRC_FREQS_CFG_P1_1333,
        {uMCTL2_FREQ1_DERATEEN, 0x00001101},
        {uMCTL2_FREQ1_DERATEINT, 0x350D70C},

        //XS 667
        LPDDR4_DDRC_FREQS_CFG_P2_667
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_1333_333_xg_1g[] = {
	LPDDR4_DDRC_FREQS_CFG_P1_1333,

	//XS 333
	LPDDR4_DDRC_FREQS_CFG_P2_333
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_1333_333_xg_2g[] = {
	LPDDR4_DDRC_FREQS_CFG_P1_1333_2G,

	//XS 333
	LPDDR4_DDRC_FREQS_CFG_P2_333_2G
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_333_jh32[] = {
	// H9HCNNNBKUMLHR
	//JH P1 333
	{uMCTL2_FREQ1_DERATEINT, 0xD4239E},
	{uMCTL2_FREQ1_PWRTMG, 0x40fe10},
	{uMCTL2_FREQ1_RANKCTL, 0xf460},
	{uMCTL2_FREQ1_RFSHTMG, 0x000A0018},//Janice
	{uMCTL2_FREQ1_DRAMTMG0, 0x0A040204},
	{uMCTL2_FREQ1_DRAMTMG1, 0x00030406},
	{uMCTL2_FREQ1_DRAMTMG2, 0x0203080B},
	{uMCTL2_FREQ1_DRAMTMG3, 0x00505000},
	{uMCTL2_FREQ1_DRAMTMG4, 0x02040203},
	{uMCTL2_FREQ1_DRAMTMG5, 0x02030202},
	{uMCTL2_FREQ1_DRAMTMG6, 0x00000004},
	{uMCTL2_FREQ1_DRAMTMG7, 0x00000302},
	{uMCTL2_FREQ1_DRAMTMG8, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG9, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG10, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG11, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG12, 0x00020000},
	{uMCTL2_FREQ1_DRAMTMG13, 0x00100002},
	{uMCTL2_FREQ1_DRAMTMG14, 0x00000018},//Janice
	{uMCTL2_FREQ1_ZQCTL0, 0xC0540004},//enable ZQCL/MPC(ZQ calibration)
	{uMCTL2_FREQ1_DFITMG0, 0x03818200},
	{uMCTL2_FREQ1_DFITMG1, 0x000D0202},
	{uMCTL2_FREQ1_DFITMG2, 0x00000100},
	{uMCTL2_FREQ1_ODTCFG, 0x00000000},
	{uMCTL2_FREQ1_INIT3, 0x00040000},
	{uMCTL2_FREQ1_INIT4, 0x00B30000},
	{uMCTL2_FREQ1_INIT6, 0x00430054},
	{uMCTL2_FREQ1_INIT7, 0x0014005C},
	{uMCTL2_FREQ1_RFSHTMG1, 0x00080000},
	{uMCTL2_FREQ1_RFSHCTL0, 0x00210000},
	{uMCTL2_FREQ1_DERATEEN, 0x00001021},
};

struct DRAM_CFG_PARAM lpddr4_ddrc_freqs_cfg_333_xg32_a1ra_2g[] = {
	// K4F6E3S4HMMGCJ
	//XG 2GB P1 333
	{uMCTL2_FREQ1_DERATEINT, 0xD4239E},
	{uMCTL2_FREQ1_PWRTMG, 0x40fe10},
	{uMCTL2_FREQ1_RANKCTL, 0xf460},
	{uMCTL2_FREQ1_RFSHTMG, 0x000A0018},
	{uMCTL2_FREQ1_DRAMTMG0, 0x0A040204},
	{uMCTL2_FREQ1_DRAMTMG1, 0x00030406},
	{uMCTL2_FREQ1_DRAMTMG2, 0x0203080B},
	{uMCTL2_FREQ1_DRAMTMG3, 0x00505000},
	{uMCTL2_FREQ1_DRAMTMG4, 0x02040203},
	{uMCTL2_FREQ1_DRAMTMG5, 0x02030202},
	{uMCTL2_FREQ1_DRAMTMG6, 0x00000004},
	{uMCTL2_FREQ1_DRAMTMG7, 0x00000302},
	{uMCTL2_FREQ1_DRAMTMG8, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG9, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG10, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG11, 0x00000000},
	{uMCTL2_FREQ1_DRAMTMG12, 0x00020000},
	{uMCTL2_FREQ1_DRAMTMG13, 0x00100002},
	{uMCTL2_FREQ1_DRAMTMG14, 0x00000018},
	{uMCTL2_FREQ1_ZQCTL0, 0xC0540004},
	{uMCTL2_FREQ1_DFITMG0, 0x03818200},
	{uMCTL2_FREQ1_DFITMG1, 0x000D0202},
	{uMCTL2_FREQ1_DFITMG2, 0x00000100},
	{uMCTL2_FREQ1_ODTCFG, 0x00000000},
	{uMCTL2_FREQ1_INIT3, 0x00040000},
	{uMCTL2_FREQ1_INIT4, 0x00B30000},
	{uMCTL2_FREQ1_INIT6, 0x00430054},
	{uMCTL2_FREQ1_INIT7, 0x0014005C},
	{uMCTL2_FREQ1_RFSHTMG1, 0x00080000},
	{uMCTL2_FREQ1_RFSHCTL0, 0x00210000},
	{uMCTL2_FREQ1_DERATEEN, 0x00001021},
};

struct DRAM_CFG_PARAM lpddr4_ddrc_cfg_hynix[] = {
	{uMCTL2_DRAMTMG2, DRAMTMG2_LPDDR4_HYNIX},
	{uMCTL2_RFSHTMG, RFSHTMG_LPDDR4_HYNIX},
	{uMCTL2_RFSHTMG1, RFSHTMG1_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrc_cfg_hynix(void)
{
	return ARRAY_SIZE(lpddr4_ddrc_cfg_hynix);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_hynix[] = {
	{uMCTL2_DRAMTMG2, DRAMTMG2_LPDDR4_HYNIX_3200},
	{uMCTL2_RFSHTMG, RFSHTMG_LPDDR4_HYNIX_3200},
};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg_hynix(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg_hynix);
}


struct DRAM_CFG_PARAM lpddr4_100_ddrc_cfg[] = {
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x800C0004},
//	{uMCTL2_INIT0, 0x00010031},
//	{uMCTL2_INIT1, 0x00050000},
////	{uMCTL2_INIT2, 0x4205},
//	{uMCTL2_INIT3, 0x00040000},
//	{uMCTL2_INIT4, 0x00A30020},
//	{uMCTL2_INIT5, 0x00000000},
//	{uMCTL2_INIT6, 0x0066004C},
//	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_INIT0, 0x00020002},
	{uMCTL2_INIT1, 0x00080000},
//	{uMCTL2_INIT2, 0x4205},
	{uMCTL2_INIT3, 0x00040000},
	{uMCTL2_INIT4, 0x00310010},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0000006d},
	{uMCTL2_INIT7, 0x0000006D},
	{uMCTL2_DRAMTMG0, 0x0A010002},
	{uMCTL2_DRAMTMG1, 0x00030404},
	{uMCTL2_DRAMTMG2, 0x0203070B},
	{uMCTL2_DRAMTMG3, 0x00505000},
	{uMCTL2_DRAMTMG4, 0x02030202},
	{uMCTL2_DRAMTMG5, 0x02030303},
	{uMCTL2_DRAMTMG6, 0x00000004},
	{uMCTL2_DRAMTMG7, 0x00000302},
	{uMCTL2_DRAMTMG13, 0x00100002},
	{uMCTL2_DRAMTMG14, 0x00000008},

	{uMCTL2_ZQCTL0, 0xc0190004},
	{uMCTL2_ZQCTL1, 0x00201b46},

	{uMCTL2_DFITMG0, 0x03818200},
	{uMCTL2_DFITMG1, 0x000B0202},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00000100},
	{uMCTL2_DFIPHYMSTR, 0x1},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 100 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_100_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_100_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_667_ddrc_cfg[] = {
	{uMCTL2_RFSHCTL0, 0x210000},
	{uMCTL2_RFSHTMG, 0x14002f},
	{uMCTL2_RFSHTMG1, 0x0f0000},
	{uMCTL2_CRCPARCTL1, 0x1000},
	{uMCTL2_INIT2, 0x4205},
	{uMCTL2_INIT3, 0x140009},
	{uMCTL2_INIT4, 0x310000},
	{uMCTL2_INIT6, 0x64004d},
	{uMCTL2_INIT7, 0x4004f},
	{uMCTL2_DRAMTMG0, 0xb070b07},
	{uMCTL2_DRAMTMG1, 0x3040b},
	{uMCTL2_DRAMTMG2, 0x305080c},
	{uMCTL2_DRAMTMG3, 0x505006},
	{uMCTL2_DRAMTMG4, 0x5040305},
	{uMCTL2_DRAMTMG5, 0x2030303},
	{uMCTL2_DRAMTMG6, 0x1010004},
	{uMCTL2_DRAMTMG7, 0x302},
	{uMCTL2_DRAMTMG13, 0xc0100002},
	{uMCTL2_DRAMTMG14, 0x30},
	{uMCTL2_DFITMG0, 0x3858202},
	{uMCTL2_DFITMG1, 0xa0202},
	{uMCTL2_DFILPCFG0, 0x3614101},
	{uMCTL2_DFITMG2, 0x502},
	{uMCTL2_ADDRMAP1, 0x50505},
	{uMCTL2_ADDRMAP3, 0x14141400},
	{uMCTL2_ADDRMAP5, 0x4040404},
	{uMCTL2_ADDRMAP6, 0x4040404},
	{uMCTL2_ADDRMAP9, 0x4040404},
	{uMCTL2_ADDRMAP10, 0x4040404},
	{uMCTL2_ADDRMAP11, 0x4},
	{uMCTL2_ADDRMAP2, 0x0},
	{uMCTL2_ADDRMAP4, 0x1f1f},
	{uMCTL2_SCHED, 0x20003601},
	{uMCTL2_SBRCTL, 0x3f41},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 667 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_667_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_667_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_2666_ddrc_cfg[] = {
#if (XH_ENABLE == 1)
	#if defined(XH_LP4_26_A1)
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x8145003D},
	{uMCTL2_DRAMTMG0, 0x1C1B161D},
	{uMCTL2_DRAMTMG1, 0x00060629},
	{uMCTL2_DRAMTMG2, 0x0B0C0B17},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x10100002},
	{uMCTL2_DRAMTMG14, 0x0000007E},

	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938212},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001312},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440064},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},

	{uMCTL2_DBICTL, 0x00000002},

	#else
	//Ctrl_XH_LP4_26_A0
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145003D},
	{uMCTL2_DRAMTMG0, 0x171B161D},
	{uMCTL2_DRAMTMG1, 0x00060629},
	{uMCTL2_DRAMTMG2, 0x060C1012},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x0000007E},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0062002E},
	{uMCTL2_INIT7, 0x0004002E},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	#endif
#elif ( JH_ENABLE == 1 )
//Ctrl_JH_LP4_26_A0
    /*
	//2667
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145005E},
	{uMCTL2_DRAMTMG0, 0x171B161D},
	{uMCTL2_DRAMTMG1, 0x00100629},
	{uMCTL2_DRAMTMG2, 0x060C1012},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x000000C0},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020517},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	*/
	//2666
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145005E},
	{uMCTL2_DRAMTMG0, 0x171B161C},
	{uMCTL2_DRAMTMG1, 0x00050528},
	{uMCTL2_DRAMTMG2, 0x060C1112},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0C04070D},
	{uMCTL2_DRAMTMG5, 0x02040A0A},
	{uMCTL2_DRAMTMG6, 0x00000006},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x000000C0},
	{uMCTL2_ZQCTL0, 0xC29B0014},
	{uMCTL2_ZQCTL1, 0x0222D727},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020516},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003C0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001302},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},

	{uMCTL2_DBICTL, 0x00000002},
#elif ( XS_ENABLE == 1 )
	#if defined(XS_LP4_26_A0R)
    //2666
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145003C},
	{uMCTL2_DRAMTMG0, 0x171B161C},
	{uMCTL2_DRAMTMG1, 0x00050528},
	{uMCTL2_DRAMTMG2, 0x060C1112},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0C04070D},
	{uMCTL2_DRAMTMG5, 0x02040A0A},
	{uMCTL2_DRAMTMG6, 0x00000006},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x0000007D},
	{uMCTL2_ZQCTL0, 0xC29B0014},
	{uMCTL2_ZQCTL1, 0x0222D727},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020516},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003C0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	{uMCTL2_PWRTMG, 0x154704},//15: enable self-refresh when no command over 1ms for power saving; 40: default value
    #endif

#else //( CVB_M_ENABLE == 1 )
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x8145005E},
	{uMCTL2_DRAMTMG0, 0x171B161D},
	{uMCTL2_DRAMTMG1, 0x00060629},
	{uMCTL2_DRAMTMG2, 0x060C1012},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x000000C0},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC0020517},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 2666 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_2666_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_2666_ddrc_cfg_micron[] = {
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x8145005E},
	{uMCTL2_DRAMTMG0, 0x171B161D},
	{uMCTL2_DRAMTMG1, 0x00060629},
	{uMCTL2_DRAMTMG2, 0x060C1012},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x000000C0},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC0020517},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
};

uint32_t get_sizeof_lpddr4_2666_ddrc_cfg_micron(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrc_cfg_micron);
}


struct DRAM_CFG_PARAM lpddr4_2666_ddrc_cfg_xh[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145003D},
	{uMCTL2_DRAMTMG0, 0x1C1B161D},
	{uMCTL2_DRAMTMG1, 0x00060629},
	{uMCTL2_DRAMTMG2, 0x0B0C0B17},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x10100002},
	{uMCTL2_DRAMTMG14, 0x0000007E},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938212},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001312},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440064},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
};

uint32_t get_sizeof_lpddr4_2666_ddrc_cfg_xh(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrc_cfg_xh);
}

struct DRAM_CFG_PARAM lpddr4_2666_ddrc_cfg_jh[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145005E},
	{uMCTL2_DRAMTMG0, 0x171B161D},
	{uMCTL2_DRAMTMG1, 0x00100629},
	{uMCTL2_DRAMTMG2, 0x060C1012},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0D04070D},
	{uMCTL2_DRAMTMG5, 0x02040B0B},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x000000C0},
	{uMCTL2_ZQCTL0, 0xC29B0015},
	{uMCTL2_ZQCTL1, 0x0222D76D},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003D0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
};

uint32_t get_sizeof_lpddr4_2666_ddrc_cfg_jh(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrc_cfg_jh);
}

struct DRAM_CFG_PARAM lpddr4_2666_ddrc_cfg_xg26_a1r[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x8145003C},
	{uMCTL2_DRAMTMG0, 0x171B161C},
	{uMCTL2_DRAMTMG1, 0x00050528},
	{uMCTL2_DRAMTMG2, 0x060C1112},
	{uMCTL2_DRAMTMG3, 0x00A0A000},
	{uMCTL2_DRAMTMG4, 0x0C04070D},
	{uMCTL2_DRAMTMG5, 0x02040A0A},
	{uMCTL2_DRAMTMG6, 0x00000006},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0B100002},
	{uMCTL2_DRAMTMG14, 0x0000007D},
	{uMCTL2_ZQCTL0, 0x829B0014},
	{uMCTL2_ZQCTL1, 0x0222D727},
	{uMCTL2_DFITMG0, 0x04938208},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007140},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001308},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020516},
	{uMCTL2_INIT1, 0x00830000},
	{uMCTL2_INIT3, 0x00440024},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x003C0000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001323},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	{uMCTL2_PWRTMG, 0x154704},//15: enable self-refresh when no command over 1ms for power saving; 40: default value
};
uint32_t get_sizeof_lpddr4_2666_ddrc_cfg_xg26_a1r(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrc_cfg_xg26_a1r);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg[] = {
#if (XH_ENABLE == 1)
	#if defined(XH_LP4_32_A1)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x20201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x0D0E0C1A},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x12100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x04978216},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001716},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054006D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},

	#elif defined(XH_LP4_32_A1R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x20201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x0D0E0C1A},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x12100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x04978216},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001716},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054006D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303}, //enable derating
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},

    #else
	//Ctrl_XH_LP4_32_A0
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00440028},
	{uMCTL2_INIT7, 0x00040028},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	#endif

#elif ( JH_ENABLE == 1)
	#if defined(JH_LP4_32_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860070},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303}, //enable derating
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
    #else
	//Ctrl_JH_LP4_32_A0
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860070},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	#endif
#elif ( XS_ENABLE == 1)
	#if defined(XS_LP4_32_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0004004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	#elif defined(XS_LP4_32_A1R)
	//Set B
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x20201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x0D0E0C1A},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x12100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x04978216},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001716},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054006D},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0004004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	#elif defined(XS_LP4_16Gb_32_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860070},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
    #endif
#elif ( CVB_M_ENABLE == 1)
	#if defined(M_LP4_16Gb_32_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860070},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	#else
	//M_LP4_32_A0
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x81860070},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	#endif
#else
	{uMCTL2_MRCTRL0, 0x6030},
	{uMCTL2_MRCTRL1, 0x686},
	{uMCTL2_MRCTRL2, 0xf2c5127a},
	{uMCTL2_DERATEEN, 0x1202},
	{uMCTL2_DERATEINT, 0xb383505f},
	{uMCTL2_PWRTMG, 0x400804},
	{uMCTL2_HWLPCTL, 0xc20002},
	{uMCTL2_RFSHCTL0, 0x210004},//PC 0318 update
	{uMCTL2_RFSHCTL1, 0x2001c},
	{uMCTL2_RFSHTMG, 0x6100e0},
	{uMCTL2_RFSHTMG1, 0x480000},
	{uMCTL2_ECCCFG0, 0x33f7f50},
	{uMCTL2_ECCCFG1, 0x7a2},
	{uMCTL2_INIT2, 0x205},
	{uMCTL2_INIT3, 0x54002d},
	{uMCTL2_INIT4, 0x300000},
	{uMCTL2_INIT5, 0x40009},
	{uMCTL2_RANKCTL, 0x8ff},
	{uMCTL2_DRAMTMG0, 0x1a203622},
	{uMCTL2_DRAMTMG1, 0x60630},
	{uMCTL2_DRAMTMG2, 0x70e0f14},
	{uMCTL2_DRAMTMG3, 0xb0c006},
	{uMCTL2_DRAMTMG4, 0xf04080f},
	{uMCTL2_DRAMTMG5, 0x2040c0c},
	{uMCTL2_DRAMTMG6, 0x1010007},
	{uMCTL2_DRAMTMG7, 0x402},
	{uMCTL2_DRAMTMG9, 0x4000000f},
	{uMCTL2_DRAMTMG10, 0x20a04},
	{uMCTL2_DRAMTMG11, 0x68010003},
	{uMCTL2_DRAMTMG13, 0xc100002},
	{uMCTL2_DRAMTMG14, 0xe6},
	{uMCTL2_ZQCTL0, 0xd3200018},
	{uMCTL2_ZQCTL1, 0x2851e48},
	{uMCTL2_DFITMG0, 0x497820a},
	{uMCTL2_DFITMG1, 0x90303},
	{uMCTL2_DFILPCFG0, 0x3808001},
	{uMCTL2_DFILPCFG1, 0x1},
	{uMCTL2_DFIUPD0, 0x80400018},
	{uMCTL2_DFIUPD1, 0x7d00f9},
	{uMCTL2_DFITMG2, 0x170a},
	{uMCTL2_ODTCFG, 0x6080a08},
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 3200 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_jh32_a1ra[] = {
	//JH_LP4_32_B0AR, use all bank refresh
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x006100E0},
	{uMCTL2_DRAMTMG0, 0x1B201A22},
	{uMCTL2_DRAMTMG1, 0x00060633},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F040812},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0,  0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg_jh32_a1ra(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg_jh32_a1ra);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_xg32_a1r[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	//{uMCTL2_DFITMG0, 0x0497820A},
	//{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFITMG0, 0x0397820A},//Janice 2
	{uMCTL2_DFITMG1, 0x000D0202},
	{uMCTL2_DFILPCFG0, 0x03007140},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC0020928},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0004004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	{uMCTL2_PWRTMG, 0x154704},

};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg_xg32_a1r(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg_xg32_a1r);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_xg32_a1ra_2g[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x006100E0},
	{uMCTL2_DRAMTMG0, 0x1B201A22},
	{uMCTL2_DRAMTMG1, 0x00060633},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F040812},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007140},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	{uMCTL2_PWRTMG, 0x154704},
};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg_xg32_a1ra_2g(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg_xg32_a1ra_2g);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_js32_a17ra_4g[] = {
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x006100E0},
	{uMCTL2_DRAMTMG0, 0x1B201A22},
	{uMCTL2_DRAMTMG1, 0x00060633},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F040812},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30000},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00540051},
	{uMCTL2_INIT7, 0x00140054},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_DERATEEN, 0x00001213},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000003},
};

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_L4M32GR1_M32_A17RA_4g[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x00610130},
	{uMCTL2_DRAMTMG0, 0x1B201A22},
	{uMCTL2_DRAMTMG1, 0x00060633},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F040812},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x00000136},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30000},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00540051},
	{uMCTL2_INIT7, 0x00140054},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F07},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000003},
};

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_L4M16G_M32_A1RA[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x006100E0},
	{uMCTL2_DRAMTMG0, 0x1B201A22},
	{uMCTL2_DRAMTMG1, 0x00060633},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F040812},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x000000E6},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210000},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
};

struct DRAM_CFG_PARAM lpddr4_3200_ddrc_cfg_L4M8GR1_M32_A17R_WDQS[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81860048},
	{uMCTL2_DRAMTMG0, 0x1A201A22},
	{uMCTL2_DRAMTMG1, 0x00060630},
	{uMCTL2_DRAMTMG2, 0x070E1214},
	{uMCTL2_DRAMTMG3, 0x00C0C000},
	{uMCTL2_DRAMTMG4, 0x0F04080F},
	{uMCTL2_DRAMTMG5, 0x02040C0C},
	{uMCTL2_DRAMTMG6, 0x00000007},
	{uMCTL2_DRAMTMG7, 0x00000402},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0C100002},
	{uMCTL2_DRAMTMG14, 0x00000096},
	{uMCTL2_ZQCTL0, 0xC3200018},
	{uMCTL2_ZQCTL1, 0x028368CE},
	{uMCTL2_DFITMG0, 0x0497820A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x0000170A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002061B},
	{uMCTL2_INIT1, 0x009D0000},
	{uMCTL2_INIT3, 0x0054002D},
	{uMCTL2_INIT4, 0x00B30000},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00540051},
	{uMCTL2_INIT7, 0x00140054},
	{uMCTL2_RFSHTMG1, 0x00480000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001223},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000003},
};

uint32_t get_sizeof_lpddr4_3200_ddrc_cfg_L4M32GR1_M32_A17RA_4g(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrc_cfg_L4M32GR1_M32_A17RA_4g);
}

struct DRAM_CFG_PARAM lpddr4_3600_ddrc_cfg[] = {
#if (CVB_M_ENABLE == 1)

#elif ( JH_ENABLE == 1)
	//JH_LP4_36_A0
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81B7007E},
	{uMCTL2_DRAMTMG0, 0x1D241E26},
	{uMCTL2_DRAMTMG1, 0x00070736},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00D0D000},
	{uMCTL2_DRAMTMG4, 0x11040911},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x00000103},
	{uMCTL2_ZQCTL0, 0xC384001B},
	{uMCTL2_ZQCTL1, 0x02D3D5E7},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC00206DE},
	{uMCTL2_INIT1, 0x00B00000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00510000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001403},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080202},
	{uMCTL2_ADDRMAP2, 0x02020000},
	{uMCTL2_ADDRMAP3, 0x02020202},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},

#elif ( XS_ENABLE == 1)
	#if defined(XS_LP4_36_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81B70051},
	{uMCTL2_DRAMTMG0, 0x1D241E26},
	{uMCTL2_DRAMTMG1, 0x00070736},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00D0D000},
	{uMCTL2_DRAMTMG4, 0x11040911},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x000000A9},
	{uMCTL2_ZQCTL0, 0xC384001B},
	{uMCTL2_ZQCTL1, 0x02D3D5E7},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC00206DE},
	{uMCTL2_INIT1, 0x00B00000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0004004C},
	{uMCTL2_RFSHTMG1, 0x00510000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001403},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	#elif defined(XS_LP4_16Gb_36_A0R)
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81B7007E},
	{uMCTL2_DRAMTMG0, 0x1D241E26},
	{uMCTL2_DRAMTMG1, 0x00070736},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00D0D000},
	{uMCTL2_DRAMTMG4, 0x11040911},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x00000103},
	{uMCTL2_ZQCTL0, 0xC384001B},
	{uMCTL2_ZQCTL1, 0x02D3D5E7},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC00206DE},
	{uMCTL2_INIT1, 0x00B00000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00430054},
	{uMCTL2_INIT7, 0x0014005C},
	{uMCTL2_RFSHTMG1, 0x00510000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
	#endif
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 3600 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3600_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3600_ddrc_cfg);
}

struct DRAM_CFG_PARAM lpddr4_3600_ddrc_cfg_xg36_a17r_2g[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81B7007E},
	{uMCTL2_DRAMTMG0, 0x1D241E26},
	{uMCTL2_DRAMTMG1, 0x00070736},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00D0D000},
	{uMCTL2_DRAMTMG4, 0x11040911},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x00000103},
	{uMCTL2_ZQCTL0, 0xC384001B},
	{uMCTL2_ZQCTL1, 0x02D3D5E7},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC00206DE},
	{uMCTL2_INIT1, 0x00B00000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x00430054},
	{uMCTL2_INIT7, 0x0014005C},
	{uMCTL2_RFSHTMG1, 0x00510000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001303},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},
};

uint32_t get_sizeof_lpddr4_3600_ddrc_cfg_xg36_a17r_2g(void)
{
	return ARRAY_SIZE(lpddr4_3600_ddrc_cfg_xg36_a17r_2g);
}

struct DRAM_CFG_PARAM lpddr4_3600_ddrc_cfg_xg36_a17r[] = {
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81B70051},
	{uMCTL2_DRAMTMG0, 0x1D241E26},
	{uMCTL2_DRAMTMG1, 0x00070736},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00D0D000},
	{uMCTL2_DRAMTMG4, 0x11040911},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x000000A9},
	{uMCTL2_ZQCTL0, 0xC384001B},
	{uMCTL2_ZQCTL1, 0x02D3D5E7},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0x20400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},

	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC00206DE},
	{uMCTL2_INIT1, 0x00B00000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00B30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0004004C},
	{uMCTL2_RFSHTMG1, 0x00510000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_DERATEEN, 0x00001403},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x0F070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
	{uMCTL2_DBICTL, 0x00000002},

};

uint32_t get_sizeof_lpddr4_3600_ddrc_cfg_xg36_a17r(void)
{
	return ARRAY_SIZE(lpddr4_3600_ddrc_cfg_xg36_a17r);
}

struct DRAM_CFG_PARAM lpddr4_3733_ddrc_cfg[] = {
#if (CVB_M_ENABLE == 1)
	//M_LP4_37_A0
	{uMCTL2_MSTR, 0x83080020},
	{uMCTL2_RFSHTMG, 0x81C70083},
	{uMCTL2_DRAMTMG0, 0x1E261F28},
	{uMCTL2_DRAMTMG1, 0x00070738},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00E0E000},
	{uMCTL2_DRAMTMG4, 0x11040A12},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x0000010D},
	{uMCTL2_ZQCTL0, 0xC3A6001C},
	{uMCTL2_ZQCTL1, 0x02F3FA2E},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00002211},
	{uMCTL2_INIT0, 0xC002071F},
	{uMCTL2_INIT1, 0x00B70000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00540000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F17},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#elif ( JH_ENABLE == 1)
	//JH_LP4_37_A0
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81C70083},
	{uMCTL2_DRAMTMG0, 0x1E261F28},
	{uMCTL2_DRAMTMG1, 0x00070738},
	{uMCTL2_DRAMTMG2, 0x08101416},
	{uMCTL2_DRAMTMG3, 0x00E0E000},
	{uMCTL2_DRAMTMG4, 0x11040A12},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x0D100002},
	{uMCTL2_DRAMTMG14, 0x0000010D},
	{uMCTL2_ZQCTL0, 0xC3A6001C},
	{uMCTL2_ZQCTL1, 0x02F3FA2E},
	{uMCTL2_DFITMG0, 0x049B820C},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B0C},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002071F},
	{uMCTL2_INIT1, 0x00B70000},
	{uMCTL2_INIT3, 0x00640036},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00540000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},
#elif ( XH_ENABLE == 1)
    #if defined(XH_LP4_37_A1)
	//XH_LP4_37_A1
	{uMCTL2_MSTR, 0x81080020},
	{uMCTL2_RFSHTMG, 0x81C70054},
	{uMCTL2_DRAMTMG0, 0x25261F28},
	{uMCTL2_DRAMTMG1, 0x00070738},
	{uMCTL2_DRAMTMG2, 0x0F100D1D},
	{uMCTL2_DRAMTMG3, 0x00E0E000},
	{uMCTL2_DRAMTMG4, 0x11040A12},
	{uMCTL2_DRAMTMG5, 0x02050E0E},
	{uMCTL2_DRAMTMG6, 0x00000008},
	{uMCTL2_DRAMTMG7, 0x00000502},
	{uMCTL2_DRAMTMG8, 0x00000000},
	{uMCTL2_DRAMTMG9, 0x00000000},
	{uMCTL2_DRAMTMG10, 0x00000000},
	{uMCTL2_DRAMTMG11, 0x00000000},
	{uMCTL2_DRAMTMG12, 0x00020000},
	{uMCTL2_DRAMTMG13, 0x14100002},
	{uMCTL2_DRAMTMG14, 0x000000AF},

	{uMCTL2_ZQCTL0, 0xC3A6001C},
	{uMCTL2_ZQCTL1, 0x02F3FA2E},
	{uMCTL2_DFITMG0, 0x049B821A},
	{uMCTL2_DFITMG1, 0x000D0303},
	{uMCTL2_DFILPCFG0, 0x03007040},
	{uMCTL2_DFIUPD0, 0xA0400018},
	{uMCTL2_DFIUPD1, 0x00C200CB},
	{uMCTL2_DFITMG2, 0x00001B1A},
	{uMCTL2_DFIPHYMSTR, 0x00000001},
	{uMCTL2_ODTCFG, 0x00000000},
	{uMCTL2_ODTMAP, 0x00000011},
	{uMCTL2_INIT0, 0xC002071F},
	{uMCTL2_INIT1, 0x00B70000},
	{uMCTL2_INIT3, 0x00640076},
	{uMCTL2_INIT4, 0x00A30020},
	{uMCTL2_INIT5, 0x00000000},
	{uMCTL2_INIT6, 0x0066004C},
	{uMCTL2_INIT7, 0x0006004C},
	{uMCTL2_RFSHTMG1, 0x00540000},
	{uMCTL2_RFSHCTL0, 0x00210004},
	{uMCTL2_ADDRMAP0, 0x001F1F1F},
	{uMCTL2_ADDRMAP1, 0x00080808},
	{uMCTL2_ADDRMAP2, 0x00000000},
	{uMCTL2_ADDRMAP3, 0x00000000},
	{uMCTL2_ADDRMAP4, 0x00001F1F},
	{uMCTL2_ADDRMAP5, 0x070F0707},
	{uMCTL2_ADDRMAP6, 0x07070707},
	{uMCTL2_ADDRMAP7, 0x00000F0F},
	{uMCTL2_ADDRMAP8, 0x00003F3F},
	{uMCTL2_ADDRMAP9, 0x07070707},
	{uMCTL2_ADDRMAP10, 0x07070707},
	{uMCTL2_ADDRMAP11, 0x001F1F07},

	{uMCTL2_DBICTL, 0x00000002},
    #endif
#else
	{uMCTL2_MRCTRL0, 0x6030},
	{uMCTL2_MRCTRL1, 0x686},
	{uMCTL2_MRCTRL2, 0xf2c5127a},
	{uMCTL2_DERATEEN, 0x1302},
	{uMCTL2_DERATEINT, 0xb383505f},
	{uMCTL2_PWRTMG, 0x400804},
	{uMCTL2_HWLPCTL, 0xc20002},
	{uMCTL2_RFSHCTL0, 0x210004},//PC 0309 //different with origin hynix
	{uMCTL2_RFSHCTL1, 0x20020},
	//{uMCTL2_RFSHTMG, 0x710106},
	{uMCTL2_RFSHTMG, 0x81c70083},//PC 0309
	{uMCTL2_RFSHTMG1, 0x540000},
	{uMCTL2_ECCCFG0, 0x33f7f50},
	{uMCTL2_ECCCFG1, 0x7a2},
	{uMCTL2_ECCPOISONADDR0, 0x34d},
	{uMCTL2_ECCPOISONADDR1, 0x500d10e},
	{uMCTL2_INIT2, 0x205},
	{uMCTL2_INIT3, 0x640036},
	{uMCTL2_INIT4, 0x700000},
	{uMCTL2_INIT5, 0x4000b},
	{uMCTL2_RANKCTL, 0x9ff},
	{uMCTL2_DRAMTMG0, 0x1e263f28},
	{uMCTL2_DRAMTMG1, 0x70738},
	{uMCTL2_DRAMTMG2, 0x8101416},//PC 0309
	{uMCTL2_DRAMTMG3, 0xd0e006},
	{uMCTL2_DRAMTMG4, 0x11040a11},
	{uMCTL2_DRAMTMG5, 0x2050e0e},
	{uMCTL2_DRAMTMG6, 0x1010008},
	{uMCTL2_DRAMTMG7, 0x502},
	{uMCTL2_DRAMTMG9, 0x4000000f},
	{uMCTL2_DRAMTMG10, 0x20a04},
	{uMCTL2_DRAMTMG11, 0x68010003},
	{uMCTL2_DRAMTMG13, 0xd100002},
	{uMCTL2_DRAMTMG14, 0x10c},
	{uMCTL2_ZQCTL0, 0xd3a5001c},
	{uMCTL2_ZQCTL1, 0x2f51e48},
	{uMCTL2_DFITMG0, 0x49b820c},
	{uMCTL2_DFITMG1, 0x90303},
	{uMCTL2_DFILPCFG0, 0x3808001},
	{uMCTL2_DFILPCFG1, 0x1},
	{uMCTL2_DFIUPD0, 0x80400018},
	{uMCTL2_DFIUPD1, 0x7d00f9},
	{uMCTL2_DFITMG2, 0x1b0c},
	{uMCTL2_ODTCFG, 0x6090b0c},
	{uMCTL2_POISONCFG, 0x11},
	{uMCTL2_ADVECCINDEX, 0x1a4},
#endif
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 controller 3733 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3733_ddrc_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3733_ddrc_cfg);
}

#ifdef SPL_DDR_PKG
extern unsigned int g_ddr_vendor;

void ddr4_ddrc_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number)
{
	FILE *fp = NULL;
	int ddrc_size = 0, ddrc_freq_size = 0, ddrc_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrc_size = sizeof(ddr4_ddrc_cfg);
	printf("ddr4 ddrc size: %d\n", ddrc_size);
	fwrite(ddr4_ddrc_cfg, 2, ddrc_size / 2, fp);

	/* ddrc_freq */
	if (freq == DDR_FREQC_3200) {
		ddrc_freq_size = sizeof(ddr4_3200_ddrc_cfg);
		fwrite(ddr4_3200_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2666) {
		if (g_ddr_vendor == DDR_MANU_MICRON) {
			ddrc_freq_size = sizeof(ddr4_2666_ddrc_cfg_micron);
			fwrite(ddr4_2666_ddrc_cfg_micron, 2, ddrc_freq_size / 2, fp);
		} else if (g_ddr_vendor == DDR_MANU_SAMSUNG) {
			ddrc_freq_size = sizeof(ddr4_2666_ddrc_cfg_samsung);
			fwrite(ddr4_2666_ddrc_cfg_samsung, 2, ddrc_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_2640) {
		if (part_number == K4A4G165WF_BCTD) {
			ddrc_freq_size = sizeof(ddr4_2640_ddrc_cfg_samsung);
			fwrite(ddr4_2640_ddrc_cfg_samsung, 2, ddrc_freq_size / 2, fp);
		} else {
			printf("Not support 2640 for other DDR chips");
		}
	} else if (freq == DDR_FREQC_2400) {
		if (part_number == K4A4G165WF_BCTD) {
			ddrc_freq_size = sizeof(ddr4_2400_ddrc_cfg_D4S512M_S24_A3);
			fwrite(ddr4_2400_ddrc_cfg_D4S512M_S24_A3, 2, ddrc_freq_size / 2, fp);
		} else {
			ddrc_freq_size = sizeof(ddr4_2400_ddrc_cfg);
			fwrite(ddr4_2400_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_1600) {
		ddrc_freq_size = sizeof(ddr4_1600_ddrc_cfg);
		fwrite(ddr4_1600_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	}

	/* align 512 */
	ddrc_size = ddrc_size + ddrc_freq_size;
	if (ddrc_size % 512)
		padding_size = 512 - ((ddrc_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	hdr_uart.ddr_ddrc.addr = hdr_uart.dmem2.addr +
		ALIGN_512(hdr_uart.dmem2.size);
	hdr_uart.ddr_ddrc.size = ddrc_size;

	hdr_ddr.ddr[index].ddr_ddrc.addr = hdr_ddr.ddr[index].dmem2.addr +
		ALIGN_512(hdr_ddr.ddr[index].dmem2.size);
	hdr_ddr.ddr[index].ddr_ddrc.size = ddrc_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrc_freqs.addr = hdr_ddr.ddr[index].ddr_ddrc.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc.size);
	hdr_ddr.ddr[index].ddr_ddrc_freqs.size = ddrc_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrc_micron_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrc_size = 0, ddrc_freq_size = 0, ddrc_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrc_size = sizeof(lpddr4_ddrc_cfg);
	fwrite(lpddr4_ddrc_cfg, 2, ddrc_size / 2, fp);
	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		ddrc_freq_size = sizeof(lpddr4_3733_ddrc_cfg);
		fwrite(lpddr4_3733_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {
		if (part_number == MT53E1G32D2FW_046AUTA) {
			ddrc_freq_size = sizeof(lpddr4_3200_ddrc_cfg_L4M32GR1_M32_A17RA_4g);
			fwrite(lpddr4_3200_ddrc_cfg_L4M32GR1_M32_A17RA_4g, 2, ddrc_freq_size / 2, fp);
		} else if (part_number == MT53D512M32D2DT_046AAT) {
			ddrc_freq_size = sizeof(lpddr4_3200_ddrc_cfg_L4M16G_M32_A1RA);
			fwrite(lpddr4_3200_ddrc_cfg_L4M16G_M32_A1RA, 2, ddrc_freq_size / 2, fp);
		}  else if (part_number == MT53E256M32D2DS_053AAT)  {
			ddrc_freq_size = sizeof(lpddr4_3200_ddrc_cfg_L4M8GR1_M32_A17R_WDQS);
			fwrite(lpddr4_3200_ddrc_cfg_L4M8GR1_M32_A17R_WDQS, 2, ddrc_freq_size / 2, fp);
		} else {
			ddrc_freq_size = sizeof(lpddr4_3200_ddrc_cfg);
			fwrite(lpddr4_3200_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_2666) {
		ddrc_freq_size = sizeof(lpddr4_2666_ddrc_cfg_micron);
		fwrite(lpddr4_2666_ddrc_cfg_micron, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_667) {
		ddrc_freq_size = sizeof(lpddr4_667_ddrc_cfg);
		fwrite(lpddr4_667_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_100) {
		ddrc_freq_size = sizeof(lpddr4_100_ddrc_cfg);
		fwrite(lpddr4_100_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	}

	/* align 512 */
	ddrc_size = ddrc_size + ddrc_freq_size;
	if (ddrc_size % 512)
		padding_size = 512 - ((ddrc_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	printf("lpddr4 micron ddrc size: %d\n", ddrc_size);

	hdr_uart.ddr_ddrc.addr = hdr_uart.dmem2.addr +
		ALIGN_512(hdr_uart.dmem2.size);
	hdr_uart.ddr_ddrc.size = ddrc_size;

	hdr_ddr.ddr[index].ddr_ddrc.addr = hdr_ddr.ddr[index].dmem2.addr +
		ALIGN_512(hdr_ddr.ddr[index].dmem2.size);
	hdr_ddr.ddr[index].ddr_ddrc.size = ddrc_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrc_freqs.addr = hdr_ddr.ddr[index].ddr_ddrc.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc.size);
	hdr_ddr.ddr[index].ddr_ddrc_freqs.size = ddrc_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrc_hynix_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrc_size = 0, ddrc_hynix_size = 0, ddrc_freq_size = 0, ddrc_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;
	int32_t tmp_dfs_size = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrc_size = sizeof(lpddr4_ddrc_cfg);
	fwrite(lpddr4_ddrc_cfg, 2, ddrc_size / 2, fp);

	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		ddrc_freq_size = sizeof(lpddr4_3733_ddrc_cfg);
		fwrite(lpddr4_3733_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {

		if (part_number == H9HCNNNBKUMLHR) {
			/* JH32_A1 */
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg_jh32_a1ra);
			fwrite(lpddr4_3200_ddrc_cfg_jh32_a1ra, 2,
				sizeof(lpddr4_3200_ddrc_cfg_jh32_a1ra) / 2, fp);
		} else {
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg);
			fwrite(lpddr4_3200_ddrc_cfg, 2,
				sizeof(lpddr4_3200_ddrc_cfg) / 2, fp);
		}
	} else if (freq == DDR_FREQC_2666) {
		if (part_number == H9HCNNN8KUMLHR) {
			/* XH26_B13 */
			ddrc_freq_size = sizeof(lpddr4_2666_ddrc_cfg_xh);
			fwrite(lpddr4_2666_ddrc_cfg_xh, 2, ddrc_freq_size / 2, fp);
		} else if (part_number == H9HCNNNBKUMLHR) {
			/* JH26_A3 */
			ddrc_freq_size = sizeof(lpddr4_2666_ddrc_cfg_jh);
			fwrite(lpddr4_2666_ddrc_cfg_jh, 2, ddrc_freq_size / 2, fp);
		} else {
			ddrc_freq_size = sizeof(lpddr4_2666_ddrc_cfg);
			fwrite(lpddr4_2666_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_667) {
		ddrc_freq_size = sizeof(lpddr4_667_ddrc_cfg);
		fwrite(lpddr4_667_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	}

	/* align 512 */
	ddrc_size = ddrc_size + ddrc_hynix_size + ddrc_freq_size;
	if (ddrc_size % 512)
		padding_size = 512 - ((ddrc_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	printf("lpddr4 hynix ddrc size: %d\n", ddrc_size);

	hdr_uart.ddr_ddrc.addr = hdr_uart.dmem2.addr +
		ALIGN_512(hdr_uart.dmem2.size);
	hdr_uart.ddr_ddrc.size = ddrc_size;

	/*dfs ddr_ddrc_freqs*/
	if (freq == DDR_FREQC_3200) {
		if (part_number == H9HCNNNBKUMLHR) {
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
					DDR_FREQC_333, 0,
					lpddr4_ddrc_freqs_cfg_333_jh32,
					lpddr4_3200_333,
					lpddr4_3200_333_cnt);
			if (tmp_dfs_size > 0)
				ddrc_dfs_size = tmp_dfs_size;
		}
	}

	if (part_number == H9HCNNNBKUMLHR) {
		for (i = 0; i < ARRAY_SIZE(lpddr4_3200_333); i++) {
			if (freq == lpddr4_3200_333[i].dfs_p0) {
				hdr_ddr.ddr_dfs[index].freq_p1 = lpddr4_3200_333[i].dfs_p1;
				hdr_ddr.ddr_dfs[index].freq_p2 = lpddr4_3200_333[i].dfs_p2;
				break;
			}
		}
	}
	hdr_ddr.ddr[index].ddr_ddrc.addr = hdr_ddr.ddr[index].dmem2.addr +
		ALIGN_512(hdr_ddr.ddr[index].dmem2.size);
	hdr_ddr.ddr[index].ddr_ddrc.size = ddrc_size;
	hdr_ddr.ddr[index].ddr_ddrc_freqs.addr = hdr_ddr.ddr[index].ddr_ddrc.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc.size);
	hdr_ddr.ddr[index].ddr_ddrc_freqs.size = ddrc_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrc_samsung_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrc_size = 0, ddrc_hynix_size = 0, ddrc_freq_size = 0, ddrc_dfs_size = 0;
	int32_t tmp_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrc_size = sizeof(lpddr4_ddrc_cfg);
	fwrite(lpddr4_ddrc_cfg, 2, ddrc_size / 2, fp);

	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		ddrc_freq_size = sizeof(lpddr4_3733_ddrc_cfg);
		fwrite(lpddr4_3733_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3600) {
		if (part_number == K4F6E3S4HMMGCJ) {
			/* XS36_A17R 2G */
			ddrc_freq_size += sizeof(lpddr4_3600_ddrc_cfg_xg36_a17r_2g);
			fwrite(lpddr4_3600_ddrc_cfg_xg36_a17r_2g, 2,
				sizeof(lpddr4_3600_ddrc_cfg_xg36_a17r_2g) / 2, fp);
		} else if (part_number == K4F8E304HBMGCJ) {
			/* XS36_A17R 1G */
			ddrc_freq_size += sizeof(lpddr4_3600_ddrc_cfg_xg36_a17r);
			fwrite(lpddr4_3600_ddrc_cfg_xg36_a17r, 2,
				sizeof(lpddr4_3600_ddrc_cfg_xg36_a17r) / 2, fp);

		} else {
			ddrc_freq_size += sizeof(lpddr4_3600_ddrc_cfg);
			fwrite(lpddr4_3600_ddrc_cfg, 2,
				sizeof(lpddr4_3600_ddrc_cfg) / 2, fp);
		}
	} else if (freq == DDR_FREQC_3200) {
		if (part_number == K4F8E304HBMGCJ) {
			/* XS32_A1R */
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg_xg32_a1r);
			fwrite(lpddr4_3200_ddrc_cfg_xg32_a1r, 2,
				sizeof(lpddr4_3200_ddrc_cfg_xg32_a1r) / 2, fp);
		} else if (part_number == K4F6E3S4HMMGCJ) {
			/* XS32_A1RA 2GB*/
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg_xg32_a1ra_2g);
			fwrite(lpddr4_3200_ddrc_cfg_xg32_a1ra_2g, 2,
				sizeof(lpddr4_3200_ddrc_cfg_xg32_a1ra_2g) / 2, fp);
		} else if (part_number == K4FBE3D4HM_THCL ) {
			/* JS32_A17RA 4GB*/
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg_js32_a17ra_4g);
			fwrite(lpddr4_3200_ddrc_cfg_js32_a17ra_4g, 2,
			sizeof(lpddr4_3200_ddrc_cfg_js32_a17ra_4g) / 2, fp);
		} else {
			ddrc_freq_size += sizeof(lpddr4_3200_ddrc_cfg);
			fwrite(lpddr4_3200_ddrc_cfg, 2,
				sizeof(lpddr4_3200_ddrc_cfg) / 2, fp);
		}
	} else if (freq == DDR_FREQC_2666) {
		if (part_number == K4F8E304HBMGCJ || part_number == K4F6E3S4HMMGCJ) {
			/* XS32_A0R */
			ddrc_freq_size += sizeof(lpddr4_2666_ddrc_cfg_xg26_a1r);
			fwrite(lpddr4_2666_ddrc_cfg_xg26_a1r, 2,
				sizeof(lpddr4_2666_ddrc_cfg_xg26_a1r) / 2, fp);
		}  else {
			ddrc_freq_size = sizeof(lpddr4_2666_ddrc_cfg);
			fwrite(lpddr4_2666_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_667) {
		ddrc_freq_size = sizeof(lpddr4_667_ddrc_cfg);
		fwrite(lpddr4_667_ddrc_cfg, 2, ddrc_freq_size / 2, fp);
	}

	/* align 512 */
	ddrc_size = ddrc_size + ddrc_hynix_size + ddrc_freq_size;
	if (ddrc_size % 512)
		padding_size = 512 - ((ddrc_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	printf("lpddr4 samsung ddrc size: %d\n", ddrc_size);
#ifdef YMODEM_BOOT
#else

	if (part_number == K4F8E304HBMGCJ && freq == DDR_FREQC_3200) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
						    DDR_FREQC_2666, DDR_FREQC_667,
						     lpddr4_ddrc_freqs_cfg_2666_667_xg_1g,
						     lpddr4_samsung_1g,
						     lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
							 DDR_FREQC_2666,
							 DDR_FREQC_333,
							 lpddr4_ddrc_freqs_cfg_2666_333_xg_1g,
							 lpddr4_samsung_1g,
							 lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;

		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
							 DDR_FREQC_1333,
							 DDR_FREQC_333,
							 lpddr4_ddrc_freqs_cfg_1333_333_xg_1g,
							 lpddr4_samsung_1g,
							 lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;
	} else if (part_number == K4F8E304HBMGCJ && freq == DDR_FREQC_2666) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,
						    DDR_FREQC_1333,
						    DDR_FREQC_667,
						    lpddr4_ddrc_freqs_cfg_1333_667_xg_1g,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,DDR_FREQC_1333,
						    DDR_FREQC_333,
						    lpddr4_ddrc_freqs_cfg_1333_333_xg_1g,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;
	} else if (part_number == K4F6E3S4HMMGCJ && freq == DDR_FREQC_3200) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200, DDR_FREQC_1333,
						     DDR_FREQC_333,
						     lpddr4_ddrc_freqs_cfg_1333_333_xg_2g,
						     lpddr4_samsung_2g,
						     lpddr4_samsung_2g_cnt);
		if (tmp_dfs_size > 0)
			ddrc_dfs_size = tmp_dfs_size;
	}
	if (part_number == K4F8E304HBMGCJ) {
		for (i = 0; i < ARRAY_SIZE(lpddr4_samsung_1g); i++) {
			if (freq == lpddr4_samsung_1g[i].dfs_p0) {
				hdr_ddr.ddr_dfs[index].freq_p1 = lpddr4_samsung_1g[i].dfs_p1;
				hdr_ddr.ddr_dfs[index].freq_p2 = lpddr4_samsung_1g[i].dfs_p2;
				break;
			}
		}
	} else if (part_number == K4F6E3S4HMMGCJ) {
		for (i = 0; i < ARRAY_SIZE(lpddr4_samsung_2g); i++) {
			if (freq == lpddr4_samsung_2g[i].dfs_p0) {
				hdr_ddr.ddr_dfs[index].freq_p1 = lpddr4_samsung_2g[i].dfs_p1;
				hdr_ddr.ddr_dfs[index].freq_p2 = lpddr4_samsung_2g[i].dfs_p2;
				printf("p1_idx:%x\n",hdr_ddr.ddr_dfs[index].freq_p1);
				printf("p2_idx:%x\n",hdr_ddr.ddr_dfs[index].freq_p2);
				break;
			}
		}
	}
#endif

	hdr_uart.ddr_ddrc.addr = hdr_uart.dmem2.addr +
		ALIGN_512(hdr_uart.dmem2.size);
	hdr_uart.ddr_ddrc.size = ddrc_size;

	hdr_ddr.ddr[index].ddr_ddrc.addr = hdr_ddr.ddr[index].dmem2.addr +
		ALIGN_512(hdr_ddr.ddr[index].dmem2.size);
	hdr_ddr.ddr[index].ddr_ddrc.size = ddrc_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrc_freqs.addr = hdr_ddr.ddr[index].ddr_ddrc.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc.size);
	hdr_ddr.ddr[index].ddr_ddrc_freqs.size = ddrc_dfs_size;
	pclose(fp);
	return;
}


#endif
